In-Ho Moon

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Logic simulation of circuit designs using on-the-fly bit reduction...
- Patent number 11,615,225
- Issue date Mar 28, 2023
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-level learning for word-level constraint solving
- Patent number 11,341,416
- Issue date May 24, 2022
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-dimensional constraint solver using modified relaxation process
- Patent number 10,762,262
- Issue date Sep 1, 2020
- Synopsys, Inc.
- In Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing x-pessimism in gate-level simulation and verification
- Patent number 8,650,513
- Issue date Feb 11, 2014
- Synopsys, Inc.
- Arturo Salz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Abstraction-based livelock/deadlock checking for hardware verification
- Patent number 8,302,044
- Issue date Oct 30, 2012
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification technique including deriving invariants from constraints
- Patent number 8,156,462
- Issue date Apr 10, 2012
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for distinguishing combinational designs
- Patent number 8,074,194
- Issue date Dec 6, 2011
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing abstraction-refinement using a lower-bound-distance to v...
- Patent number 8,032,848
- Issue date Oct 4, 2011
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for performing sequential equivalence checking on...
- Patent number 8,015,521
- Issue date Sep 6, 2011
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for distinguishing combinational designs
- Patent number 7,890,896
- Issue date Feb 15, 2011
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOGIC SIMULATION OF CIRCUIT DESIGNS USING ON-THE-FLY BIT REDUCTION...
- Publication number 20210089695
- Publication date Mar 25, 2021
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ABSTRACTION-BASED LIVELOCK/DEADLOCK CHECKING FOR HARDWARE VERIFICATION
- Publication number 20120198397
- Publication date Aug 2, 2012
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REDUCING X-PESSIMISM IN GATE-LEVEL SIMULAT...
- Publication number 20120072876
- Publication date Mar 22, 2012
- Synopsys, Inc.
- Arturo Salz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING ABSTRACTION-REFINEMENT USING A...
- Publication number 20100192114
- Publication date Jul 29, 2010
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Verification Technique Including Deriving Invariants From Constraints
- Publication number 20100083201
- Publication date Apr 1, 2010
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DISTINGUISHING COMBINATIONAL DESIGNS
- Publication number 20100017175
- Publication date Jan 21, 2010
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR PERFORMING SEQUENTIAL EQUIVALENCE CHECKING ON...
- Publication number 20090300563
- Publication date Dec 3, 2009
- Synopsys, Inc.
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for distinguishing combinational designs
- Publication number 20070118339
- Publication date May 24, 2007
- In-Ho Moon
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Logic simulation of circuit designs using on-the-fly bit reduction...

Bit-level learning for word-level constraint solving

Multi-dimensional constraint solver using modified relaxation process

Reducing x-pessimism in gate-level simulation and verification

Abstraction-based livelock/deadlock checking for hardware verification

Verification technique including deriving invariants from constraints

Method and apparatus for distinguishing combinational designs

Performing abstraction-refinement using a lower-bound-distance to v...

Method and system for performing sequential equivalence checking on...

Method and apparatus for distinguishing combinational designs

Patents Applicationslast 30 patents

LOGIC SIMULATION OF CIRCUIT DESIGNS USING ON-THE-FLY BIT REDUCTION...

ABSTRACTION-BASED LIVELOCK/DEADLOCK CHECKING FOR HARDWARE VERIFICATION

METHOD AND APPARATUS FOR REDUCING X-PESSIMISM IN GATE-LEVEL SIMULAT...

METHOD AND APPARATUS FOR PERFORMING ABSTRACTION-REFINEMENT USING A...

Verification Technique Including Deriving Invariants From Constraints

METHOD AND APPARATUS FOR DISTINGUISHING COMBINATIONAL DESIGNS

METHOD AND SYSTEM FOR PERFORMING SEQUENTIAL EQUIVALENCE CHECKING ON...

Method and apparatus for distinguishing combinational designs