Inderjit Singh

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Chip package having a cover with window
- Patent number 11,201,095
- Issue date Dec 14, 2021
- Xilinx, Inc.
- Ronilo Boja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die singulation and stacked device structures
- Patent number 11,075,117
- Issue date Jul 27, 2021
- Xilinx, Inc.
- Ganesh Hariharan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having enhanced stiffener
- Patent number 10,840,192
- Issue date Nov 17, 2020
- Xilinx, Inc.
- Nael Zohni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package assembly with composite stiffener
- Patent number 10,764,996
- Issue date Sep 1, 2020
- Xilinx, Inc.
- Ronilo Boja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package assembly with surface mounted component protection
- Patent number 10,438,863
- Issue date Oct 8, 2019
- Xilinx, Inc.
- Ronilo Boja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having an enhanced lid
- Patent number 10,043,730
- Issue date Aug 7, 2018
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterogeneous integration of integrated circuit device and companio...
- Patent number 9,865,567
- Issue date Jan 9, 2018
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer-less stack die interconnect
- Patent number 9,761,533
- Issue date Sep 12, 2017
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having enhanced lid adhesion
- Patent number 9,418,909
- Issue date Aug 16, 2016
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for providing charge protection to one or more dies during f...
- Patent number 9,385,106
- Issue date Jul 5, 2016
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package testing
- Patent number 9,341,668
- Issue date May 17, 2016
- XILNIX, INC.
- Ganesh Hariharan
- G01 - MEASURING TESTING
Information Patent Grant
Method for removing bumps from incomplete and defective interposer...
- Patent number 8,900,987
- Issue date Dec 2, 2014
- Xilinx, Inc.
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package and method of assembling an integrated c...
- Patent number 8,536,717
- Issue date Sep 17, 2013
- Xilinx, Inc.
- Shin S. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit/substrate interconnect system and method of manu...
- Patent number 8,198,727
- Issue date Jun 12, 2012
- NVIDIA Corporation
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a pad over active circuit I.C. with frame sup...
- Patent number 8,017,520
- Issue date Sep 13, 2011
- NVIDIA Corporation
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method of manufacture for interconnecting an integrated...
- Patent number 7,838,999
- Issue date Nov 23, 2010
- NVIDIA Corporation
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pad over active circuit system and method with meshed support struc...
- Patent number 7,791,193
- Issue date Sep 7, 2010
- NVIDIA Corporation
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pad over active circuit system and method with frame support structure
- Patent number 7,649,269
- Issue date Jan 19, 2010
- NVIDIA Corporation
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pad over active circuit system and method with frame support structure
- Patent number 7,495,343
- Issue date Feb 24, 2009
- NVIDIA Corporation
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pad over active circuit system and method with meshed support struc...
- Patent number 7,453,158
- Issue date Nov 18, 2008
- NVIDIA Corporation
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a pad over active circuit I.C. with meshed su...
- Patent number 7,429,528
- Issue date Sep 30, 2008
- NVIDIA Corporation
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for heat dissipation
- Patent number 7,254,033
- Issue date Aug 7, 2007
- Behdad Jafari
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHIP PACKAGE INTEGRATION WITH HYBRID BONDING
- Publication number 20230411325
- Publication date Dec 21, 2023
- Xilinx, Inc.
- Inderjit SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE SINGULATION AND STACKED DEVICE STRUCTURES
- Publication number 20190267287
- Publication date Aug 29, 2019
- Xilinx, Inc.
- Ganesh Hariharan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERPOSER-LESS STACK DIE INTERCONNECT
- Publication number 20170110407
- Publication date Apr 20, 2017
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SILICON PACKAGE ASSEMBLY HAVING AN ENHANCED LID
- Publication number 20170092619
- Publication date Mar 30, 2017
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE AND METHOD OF ASSEMBLING AN INTEGRATED C...
- Publication number 20130175709
- Publication date Jul 11, 2013
- Xilinx, Inc.
- Shin S. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR HEAT DISSIPATION
- Publication number 20080266786
- Publication date Oct 30, 2008
- Behdad Jafari
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PAD OVER ACTIVE CIRCUIT SYSTEM AND METHOD WITH MESHED SUPPORT STRUC...
- Publication number 20080067687
- Publication date Mar 20, 2008
- NVIDIA CORPORATION
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PAD OVER ACTIVE CIRCUIT SYSTEM AND METHOD WITH FRAME SUPPORT STRUCTURE
- Publication number 20080062623
- Publication date Mar 13, 2008
- NVIDIA CORPORATION
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for heat dissipation
- Publication number 20060039118
- Publication date Feb 23, 2006
- Behdad Jafari
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a pad over active circuit I.C. with meshed su...
- Publication number 20050164484
- Publication date Jul 28, 2005
- NVIDIA CORPORATION
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a pad over active circuit I.C. with frame sup...
- Publication number 20050146012
- Publication date Jul 7, 2005
- NVIDIA CORPORATION
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pad over active circuit system and method with meshed support struc...
- Publication number 20050023700
- Publication date Feb 3, 2005
- NVIDIA CORPORATION
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS

Inderjit Singh

Person

Patents Grantslast 30 patents

Chip package having a cover with window

Die singulation and stacked device structures

Stacked silicon package assembly having enhanced stiffener

Chip package assembly with composite stiffener

Chip package assembly with surface mounted component protection

Stacked silicon package assembly having an enhanced lid

Heterogeneous integration of integrated circuit device and companio...

Interposer-less stack die interconnect

Stacked silicon package assembly having enhanced lid adhesion

Method for providing charge protection to one or more dies during f...

Integrated circuit package testing

Method for removing bumps from incomplete and defective interposer...

Integrated circuit package and method of assembling an integrated c...

Integrated circuit/substrate interconnect system and method of manu...

Method of fabricating a pad over active circuit I.C. with frame sup...

System and method of manufacture for interconnecting an integrated...

Pad over active circuit system and method with meshed support struc...

Pad over active circuit system and method with frame support structure

Pad over active circuit system and method with frame support structure

Pad over active circuit system and method with meshed support struc...

Method of fabricating a pad over active circuit I.C. with meshed su...

Method and apparatus for heat dissipation

Patents Applicationslast 30 patents

CHIP PACKAGE INTEGRATION WITH HYBRID BONDING

DIE SINGULATION AND STACKED DEVICE STRUCTURES

INTERPOSER-LESS STACK DIE INTERCONNECT

STACKED SILICON PACKAGE ASSEMBLY HAVING AN ENHANCED LID

INTEGRATED CIRCUIT PACKAGE AND METHOD OF ASSEMBLING AN INTEGRATED C...

METHOD AND APPARATUS FOR HEAT DISSIPATION

PAD OVER ACTIVE CIRCUIT SYSTEM AND METHOD WITH MESHED SUPPORT STRUC...

PAD OVER ACTIVE CIRCUIT SYSTEM AND METHOD WITH FRAME SUPPORT STRUCTURE

Method and apparatus for heat dissipation

Method of fabricating a pad over active circuit I.C. with meshed su...

Method of fabricating a pad over active circuit I.C. with frame sup...

Pad over active circuit system and method with meshed support struc...