Iqbal Rajwani

Person

Roseville, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Enabling product SKUs based on chiplet configurations
- Patent number 12,141,890
- Issue date Nov 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 12,112,398
- Issue date Oct 8, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 12,056,789
- Issue date Aug 6, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy efficient memory array with optimized burst read and write d...
- Patent number 11,908,542
- Issue date Feb 20, 2024
- Intel Corporation
- Charles Augustine
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic power budget allocation in multi-processor system
- Patent number 11,874,715
- Issue date Jan 16, 2024
- Intel Corporation
- Nikos Kaburlasos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 11,763,416
- Issue date Sep 19, 2023
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 11,756,150
- Issue date Sep 12, 2023
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic power budget allocation in multi-processor system
- Patent number 11,493,974
- Issue date Nov 8, 2022
- Intel Corporation
- Nikos Kaburlasos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of System-On-Chip (SOC) architecture
- Patent number 11,410,266
- Issue date Aug 9, 2022
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling product SKUS based on chiplet configurations
- Patent number 11,386,521
- Issue date Jul 12, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for segmenting a memory array
- Patent number 11,176,990
- Issue date Nov 16, 2021
- Intel Corporation
- Bhushan M. Borole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling product SKUs based on chiplet configurations
- Patent number 10,909,652
- Issue date Feb 2, 2021
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for providing a local clock signal for...
- Patent number 10,817,012
- Issue date Oct 27, 2020
- Intel Corporation
- Iqbal R. Rajwani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of SOC architecture
- Patent number 10,803,548
- Issue date Oct 13, 2020
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for segmenting a memory array
- Patent number 10,790,010
- Issue date Sep 29, 2020
- Intel Corporation
- Bhushan M. Borole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing aging of register file keeper circuits
- Patent number 10,754,809
- Issue date Aug 25, 2020
- Intel Corporation
- Anupama A. Thaploo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic power budget allocation in multi-processor system
- Patent number 10,747,286
- Issue date Aug 18, 2020
- Intel Corporation
- Nikos Kaburlasos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power clock gate circuit
- Patent number 10,491,217
- Issue date Nov 26, 2019
- Intel Corporation
- Steven Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for providing a local clock signal for...
- Patent number 10,409,319
- Issue date Sep 10, 2019
- Intel Corporation
- Iqbal R. Rajwani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for segmenting a memory array
- Patent number 10,347,324
- Issue date Jul 9, 2019
- Intel Corporation
- Bhushan M. Borole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power switching circuitry including power-up control
- Patent number 10,333,379
- Issue date Jun 25, 2019
- Intel Corporation
- Suphachai Chai Sutanthavibul
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Reducing aging of register file keeper circuits
- Patent number 10,324,721
- Issue date Jun 18, 2019
- Intel Corporation
- Anupama A. Thaploo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared keeper and footer flip-flop
- Patent number 10,193,536
- Issue date Jan 29, 2019
- Intel Corporation
- Amit Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated clock gate circuit with embedded NOR
- Patent number 10,177,765
- Issue date Jan 8, 2019
- Intel Corporation
- Steven K. Hsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System, apparatus and method for segmenting a memory array
- Patent number 10,062,429
- Issue date Aug 28, 2018
- Intel Corporation
- Bhushan Borole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced swing bit-line apparatus and method
- Patent number 9,947,388
- Issue date Apr 17, 2018
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared keeper and footer flip-flop
- Patent number 9,859,876
- Issue date Jan 2, 2018
- Intel Corporation
- Amit Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Assist circuit for memory
- Patent number 9,685,208
- Issue date Jun 20, 2017
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Assist circuit for memory
- Patent number 9,355,694
- Issue date May 31, 2016
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power delay controlled zero sensitive sense amplifier
- Patent number 7,130,236
- Issue date Oct 31, 2006
- Intel Corporation
- Iqbal Rajwani
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
- Publication number 20250104179
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20250061535
- Publication date Feb 20, 2025
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20240013338
- Publication date Jan 11, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20240005443
- Publication date Jan 4, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO OPTIMIZE SENSE-AMP ENABLE PULSE-WIDTH IN SR...
- Publication number 20230123514
- Publication date Apr 20, 2023
- Intel Corporation
- Gururaj K. Shamanna
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM
- Publication number 20230030396
- Publication date Feb 2, 2023
- Intel Corporation
- Nikos Kaburlasos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
- Publication number 20220188967
- Publication date Jun 16, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20220180468
- Publication date Jun 9, 2022
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20220036500
- Publication date Feb 3, 2022
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
- Publication number 20210256654
- Publication date Aug 19, 2021
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENERGY EFFICIENT MEMORY ARRAY WITH OPTIMIZED BURST READ AND WRITE D...
- Publication number 20210193196
- Publication date Jun 24, 2021
- Intel Corporation
- Charles Augustine
- G11 - INFORMATION STORAGE
Information Patent Application
DISAGGREGATION OF SOC ARCHITECTURE
- Publication number 20210133913
- Publication date May 6, 2021
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Segmenting A Memory Array
- Publication number 20210065779
- Publication date Mar 4, 2021
- Intel Corporation
- Bhushan M. Borole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM
- Publication number 20210064111
- Publication date Mar 4, 2021
- Intel Corporation
- Nikos Kaburlasos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SOC ARCHITECTURE
- Publication number 20200294181
- Publication date Sep 17, 2020
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
- Publication number 20200294180
- Publication date Sep 17, 2020
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Providing A Local Clock Signal For...
- Publication number 20200019207
- Publication date Jan 16, 2020
- Intel Corporation
- Iqbal R. Rajwani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM
- Publication number 20190377395
- Publication date Dec 12, 2019
- Intel Corporation
- Nikos Kaburlasos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Segmenting A Memory Array
- Publication number 20190362772
- Publication date Nov 28, 2019
- Intel Corporation
- Bhushan M. Borole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Aging of Register File Keeper Circuits
- Publication number 20190213161
- Publication date Jul 11, 2019
- Intel Corporation
- Anupama A. Thaploo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER CLOCK GATE CIRCUIT
- Publication number 20190044511
- Publication date Feb 7, 2019
- Intel Corporation
- Steven HSU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Segmenting A Memory Array
- Publication number 20190035452
- Publication date Jan 31, 2019
- Intel Corporation
- Bhushan M. Borole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Aging of Register File Keeper Circuits
- Publication number 20180300137
- Publication date Oct 18, 2018
- Intel Corporation
- Anupama A. Thaploo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Providing A Local Clock Signal For...
- Publication number 20180299921
- Publication date Oct 18, 2018
- Iqbal R. Rajwani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER SWITCHING CIRCUITRY INCLUDING POWER-UP CONTROL
- Publication number 20180175832
- Publication date Jun 21, 2018
- Suphachai Chai Sutanthavibul
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
SHARED KEEPER AND FOOTER FLIP-FLOP
- Publication number 20180145663
- Publication date May 24, 2018
- Intel Corporation
- Amit Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CLOCK GATE CIRCUIT WITH EMBEDDED NOR
- Publication number 20180062658
- Publication date Mar 1, 2018
- Intel Corporation
- Steven K. Hsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCED SWING BIT-LINE APPARATUS AND METHOD
- Publication number 20170270998
- Publication date Sep 21, 2017
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Application
ASSIST CIRCUIT FOR MEMORY
- Publication number 20160225419
- Publication date Aug 4, 2016
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Application
ASSIST CIRCUIT FOR MEMORY
- Publication number 20150279438
- Publication date Oct 1, 2015
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE

Iqbal Rajwani

Person

Patents Grantslast 30 patents

Enabling product SKUs based on chiplet configurations

Disaggregation of system-on-chip (SOC) architecture

Disaggregation of system-on-chip (SOC) architecture

Energy efficient memory array with optimized burst read and write d...

Dynamic power budget allocation in multi-processor system

Disaggregation of system-on-chip (SOC) architecture

Disaggregation of system-on-chip (SOC) architecture

Dynamic power budget allocation in multi-processor system

Disaggregation of System-On-Chip (SOC) architecture

Enabling product SKUS based on chiplet configurations

System, apparatus and method for segmenting a memory array

Enabling product SKUs based on chiplet configurations

System, apparatus and method for providing a local clock signal for...

Disaggregation of SOC architecture

System, apparatus and method for segmenting a memory array

Reducing aging of register file keeper circuits

Dynamic power budget allocation in multi-processor system

Low-power clock gate circuit

System, apparatus and method for providing a local clock signal for...

System, apparatus and method for segmenting a memory array

Power switching circuitry including power-up control

Reducing aging of register file keeper circuits

Shared keeper and footer flip-flop

Integrated clock gate circuit with embedded NOR

System, apparatus and method for segmenting a memory array

Reduced swing bit-line apparatus and method

Shared keeper and footer flip-flop

Assist circuit for memory

Assist circuit for memory

Low power delay controlled zero sensitive sense amplifier

Patents Applicationslast 30 patents

ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

APPARATUS AND METHOD TO OPTIMIZE SENSE-AMP ENABLE PULSE-WIDTH IN SR...

DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM

ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS

ENERGY EFFICIENT MEMORY ARRAY WITH OPTIMIZED BURST READ AND WRITE D...

DISAGGREGATION OF SOC ARCHITECTURE

System, Apparatus And Method For Segmenting A Memory Array

DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM

DISAGGREGATION OF SOC ARCHITECTURE

ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS

System, Apparatus And Method For Providing A Local Clock Signal For...

DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM

System, Apparatus And Method For Segmenting A Memory Array

Reducing Aging of Register File Keeper Circuits

LOW-POWER CLOCK GATE CIRCUIT

System, Apparatus And Method For Segmenting A Memory Array

Reducing Aging of Register File Keeper Circuits

System, Apparatus And Method For Providing A Local Clock Signal For...

POWER SWITCHING CIRCUITRY INCLUDING POWER-UP CONTROL

SHARED KEEPER AND FOOTER FLIP-FLOP

INTEGRATED CLOCK GATE CIRCUIT WITH EMBEDDED NOR

REDUCED SWING BIT-LINE APPARATUS AND METHOD

ASSIST CIRCUIT FOR MEMORY

ASSIST CIRCUIT FOR MEMORY