Ish CHADHA

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Mitigating duty cycle distortion degradation due to device aging on...
- Patent number 12,027,198
- Issue date Jul 2, 2024
- NVIDIA Corporation
- Ish Chadha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reliable link management for a high-speed signaling interconnect
- Patent number 11,956,342
- Issue date Apr 9, 2024
- NVIDIA Corporation
- Seema Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital delay line calibration with duty cycle correction for high...
- Patent number 11,936,379
- Issue date Mar 19, 2024
- NVIDIA Corporation
- Ish Chadha
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frame alignment recovery for a high-speed signaling interconnect
- Patent number 11,899,609
- Issue date Feb 13, 2024
- NVIDIA Corporation
- Seema Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error rate interrupts in hardware for high-speed signaling intercon...
- Patent number 11,880,265
- Issue date Jan 23, 2024
- NVIDIA Corporation
- Adithya Hrudhayan Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link training through handshake on high-speed interconnect
- Patent number 11,784,890
- Issue date Oct 10, 2023
- NVIDIA Corporation
- Seema Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link status detection for a high-speed signaling interconnect
- Patent number 11,575,494
- Issue date Feb 7, 2023
- NVIDIA Corporation
- Seema Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronizing a high-speed signaling interconnect
- Patent number 11,569,939
- Issue date Jan 31, 2023
- NVIDIA Corporation
- Adithya Hrudhayan Krishnamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-chip package with selection logic and debug ports for testing...
- Patent number 10,317,459
- Issue date Jun 11, 2019
- NVIDIA Corporation
- Ish Chadha
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
RELIABLE LINK MANAGEMENT FOR A HIGH-SPEED SIGNALING INTERCONNECT
- Publication number 20240195599
- Publication date Jun 13, 2024
- NVIDIA Corporation
- Seema Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
FRAME ALIGNMENT RECOVERY FOR A HIGH-SPEED SIGNALING INTERCONNECT
- Publication number 20240111706
- Publication date Apr 4, 2024
- NVIDIA Corporation
- Seema Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR RATE INTERRUPTS IN HARDWARE FOR HIGH-SPEED SIGNALING INTERCON...
- Publication number 20240103951
- Publication date Mar 28, 2024
- NVIDIA Corporation
- Adithya Hrudhayan Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK TRAINING THROUGH HANDSHAKE ON HIGH-SPEED INTERCONNECT
- Publication number 20230412468
- Publication date Dec 21, 2023
- NVIDIA Corporation
- Seema Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-SPEED SIGNALING SYSTEM WITH GROUND REFERENCED SIGNALING (GRS)...
- Publication number 20230205254
- Publication date Jun 29, 2023
- NVIDIA Corporation
- Ish Chadha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RELIABLE LINK MANAGEMENT FOR A HIGH-SPEED SIGNALING INTERCONNECT
- Publication number 20230208609
- Publication date Jun 29, 2023
- NVIDIA Corporation
- Seema Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND SYSTEM FOR TRANSMITTING IN-BAND CROSS-CHIP TRIGGERS TO M...
- Publication number 20230209405
- Publication date Jun 29, 2023
- NVIDIA Corporation
- Adithya Hrudhayan Krishnamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ERROR RATE INTERRUPTS IN HARDWARE FOR HIGH-SPEED SIGNALING INTERCON...
- Publication number 20230195551
- Publication date Jun 22, 2023
- NVIDIA Corporation
- Adithya Hrudhayan Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FRAME ALIGNMENT RECOVERY FOR A HIGH-SPEED SIGNALING INTERCONNECT
- Publication number 20230195674
- Publication date Jun 22, 2023
- NVIDIA Corporation
- Seema Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK TRAINING THROUGH HANDSHAKE ON HIGH-SPEED INTERCONNECT
- Publication number 20230198852
- Publication date Jun 22, 2023
- NVIDIA Corporation
- Seema Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATING DUTY CYCLE DISTORTION DEGRADATION DUE TO DEVICE AGING ON...
- Publication number 20230162780
- Publication date May 25, 2023
- NVIDIA Corporation
- Ish CHADHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL DELAY LINE CALIBRATION WITH DUTY CYCLE CORRECTION FOR HIGH...
- Publication number 20230163764
- Publication date May 25, 2023
- NVIDIA Corporation
- Ish CHADHA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYNCHRONIZING A HIGH-SPEED SIGNALING INTERCONNECT
- Publication number 20230050617
- Publication date Feb 16, 2023
- NVIDIA Corporation
- Adithya Hrudhayan Krishnamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTI-CHIP PACKAGE WITH SELECTION LOGIC AND DEBUG PORTS FOR TESTING...
- Publication number 20180284186
- Publication date Oct 4, 2018
- NVIDIA Corporation
- Ish CHADHA
- G01 - MEASURING TESTING

Person

Patents Grantslast 30 patents

Mitigating duty cycle distortion degradation due to device aging on...

Reliable link management for a high-speed signaling interconnect

Digital delay line calibration with duty cycle correction for high...

Frame alignment recovery for a high-speed signaling interconnect

Error rate interrupts in hardware for high-speed signaling intercon...

Link training through handshake on high-speed interconnect

Link status detection for a high-speed signaling interconnect

Synchronizing a high-speed signaling interconnect

Multi-chip package with selection logic and debug ports for testing...

Patents Applicationslast 30 patents

RELIABLE LINK MANAGEMENT FOR A HIGH-SPEED SIGNALING INTERCONNECT

FRAME ALIGNMENT RECOVERY FOR A HIGH-SPEED SIGNALING INTERCONNECT

ERROR RATE INTERRUPTS IN HARDWARE FOR HIGH-SPEED SIGNALING INTERCON...

LINK TRAINING THROUGH HANDSHAKE ON HIGH-SPEED INTERCONNECT

HIGH-SPEED SIGNALING SYSTEM WITH GROUND REFERENCED SIGNALING (GRS)...

RELIABLE LINK MANAGEMENT FOR A HIGH-SPEED SIGNALING INTERCONNECT

METHOD AND SYSTEM FOR TRANSMITTING IN-BAND CROSS-CHIP TRIGGERS TO M...

ERROR RATE INTERRUPTS IN HARDWARE FOR HIGH-SPEED SIGNALING INTERCON...

FRAME ALIGNMENT RECOVERY FOR A HIGH-SPEED SIGNALING INTERCONNECT

LINK TRAINING THROUGH HANDSHAKE ON HIGH-SPEED INTERCONNECT

MITIGATING DUTY CYCLE DISTORTION DEGRADATION DUE TO DEVICE AGING ON...

DIGITAL DELAY LINE CALIBRATION WITH DUTY CYCLE CORRECTION FOR HIGH...

SYNCHRONIZING A HIGH-SPEED SIGNALING INTERCONNECT

MULTI-CHIP PACKAGE WITH SELECTION LOGIC AND DEBUG PORTS FOR TESTING...