Ishai Nachumovsky

Person

Zichron Yaakov, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Efficient test structure for non-volatile memory and other semicond...
- Patent number 6,871,307
- Issue date Mar 22, 2005
- Tower SemiconductorLtd.
- Ishai Nachumovsky
- G11 - INFORMATION STORAGE
Information Patent Grant
Mask programmable read-only memory (ROM) cell
- Patent number 6,809,948
- Issue date Oct 26, 2004
- Tower Semiconductor, Ltd.
- Ishai Nachumovsky
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-bit programmable memory cell having multiple anti-fuse elements
- Patent number 6,590,797
- Issue date Jul 8, 2003
- Tower Semiconductor Ltd.
- Ishai Nachumovsky
- G11 - INFORMATION STORAGE
Information Patent Grant
EEPROM array using 2-bit non-volatile memory cells and method of im...
- Patent number 6,256,231
- Issue date Jul 3, 2001
- Tower Semiconductor Ltd.
- Yoav Lavi
- G11 - INFORMATION STORAGE
Information Patent Grant
Area efficient column select circuitry for 2-bit non-volatile memor...
- Patent number 6,218,695
- Issue date Apr 17, 2001
- Tower Semiconductor Ltd.
- Ishai Nachumovsky
- G11 - INFORMATION STORAGE
Information Patent Grant
EEPROM array using 2-bit non-volatile memory cells with serial read...
- Patent number 6,181,597
- Issue date Jan 30, 2001
- Tower Semiconductor Ltd.
- Ishai Nachumovsky
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor chip having fieldless array with salicide gates and m...
- Patent number 6,174,758
- Issue date Jan 16, 2001
- Tower Semiconductor Ltd.
- Ishai Nachumovsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Program/erase endurance of EEPROM memory cells
- Patent number 6,157,570
- Issue date Dec 5, 2000
- Tower Semiconductor Ltd.
- Ishai Nachumovsky
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable configuration for EEPROMS including 2-bit non-volatile...
- Patent number 6,044,022
- Issue date Mar 28, 2000
- Tower Semiconductor Ltd.
- Ishai Nachumovsky
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Multi-bit programmable memory cell having multiple anti-fuse elements
- Publication number 20030223291
- Publication date Dec 4, 2003
- Tower Semiconductor, Ltd.
- Ishai Nachumovsky
- G11 - INFORMATION STORAGE
Information Patent Application
Efficient test structure for non-volatile memory and other semicond...
- Publication number 20030074611
- Publication date Apr 17, 2003
- Tower Semiconductor Ltd.
- Ishai Nachumovsky
- G11 - INFORMATION STORAGE
Information Patent Application
Two-bit split-gate non-volatile memory transistor
- Publication number 20030071288
- Publication date Apr 17, 2003
- Tower Semiconductor Ltd.
- Ishai Nachumovsky
- G11 - INFORMATION STORAGE
Information Patent Application
EEPROM array using 2 bit non-volatile memory cells and method of im...
- Publication number 20010021126
- Publication date Sep 13, 2001
- Tower Semiconductor Ltd.
- Yoav Lavi
- H01 - BASIC ELECTRIC ELEMENTS

Ishai Nachumovsky

Person

Patents Grantslast 30 patents

Efficient test structure for non-volatile memory and other semicond...

Mask programmable read-only memory (ROM) cell

Multi-bit programmable memory cell having multiple anti-fuse elements

EEPROM array using 2-bit non-volatile memory cells and method of im...

Area efficient column select circuitry for 2-bit non-volatile memor...

EEPROM array using 2-bit non-volatile memory cells with serial read...

Semiconductor chip having fieldless array with salicide gates and m...

Program/erase endurance of EEPROM memory cells

Programmable configuration for EEPROMS including 2-bit non-volatile...

Patents Applicationslast 30 patents

Multi-bit programmable memory cell having multiple anti-fuse elements

Efficient test structure for non-volatile memory and other semicond...

Two-bit split-gate non-volatile memory transistor

EEPROM array using 2 bit non-volatile memory cells and method of im...