Iwen Chao

Person

Sacramento, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Error corrected pre-read for upper page write in a multi-level cell...
- Patent number 9,543,019
- Issue date Jan 10, 2017
- Intel Corporation
- Robert E. Frickey
- G11 - INFORMATION STORAGE
Information Patent Grant
Lower page read for multi-level cell memory
- Patent number 9,524,774
- Issue date Dec 20, 2016
- Intel Corporation
- Robert E. Frickey
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically compensating for degradation of a non-volatile memory d...
- Patent number 9,418,000
- Issue date Aug 16, 2016
- Intel Corporation
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Grant
Lower page read for multi-level cell memory
- Patent number 9,236,136
- Issue date Jan 12, 2016
- Intel Corporation
- Robert E. Frickey
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for improving endurance of flash memories
- Patent number 8,400,831
- Issue date Mar 19, 2013
- Intel Corporation
- Hoon Cho
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of manufacturing semiconducting device with stacked dice
- Patent number 7,741,155
- Issue date Jun 22, 2010
- Intel Corporation
- Scott R. Sahaida
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconducting device with folded interposer
- Patent number 7,482,698
- Issue date Jan 27, 2009
- Intel Corporation
- Iwen Chao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconducting device with folded interposer
- Patent number 7,456,048
- Issue date Nov 25, 2008
- Intel Corporation
- Iwen Chao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconducting device with stacked dice
- Patent number 7,378,725
- Issue date May 27, 2008
- Intel Corporation
- Scott R. Sahaida
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconducting device with folded interposer
- Patent number 7,145,249
- Issue date Dec 5, 2006
- Intel Corporation
- Iwen Chao
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DYNAMICALLY COMPENSATING FOR DEGRADATION OF A NON-VOLATILE MEMORY D...
- Publication number 20160180958
- Publication date Jun 23, 2016
- Intel Corporation
- SHYAM SUNDER RAGHUNATHAN
- G11 - INFORMATION STORAGE
Information Patent Application
LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY
- Publication number 20160155497
- Publication date Jun 2, 2016
- Intel Corporation
- Robert E. Frickey
- G11 - INFORMATION STORAGE
Information Patent Application
LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY
- Publication number 20140173174
- Publication date Jun 19, 2014
- Robert E. Frickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTED PRE-READ FOR UPPER PAGE WRITE IN A MULTI-LEVEL CELL...
- Publication number 20140164872
- Publication date Jun 12, 2014
- Robert E. Frickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR DETERMINING ACCESS TO A MEMORY ARRAY
- Publication number 20130339603
- Publication date Dec 19, 2013
- Feng Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPROVING ENDURANCE OF FLASH MEMORIES
- Publication number 20120137048
- Publication date May 31, 2012
- Hoon Cho
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconducting device with stacked dice
- Publication number 20080280395
- Publication date Nov 13, 2008
- Intel Corporation
- Scott R. Sahaida
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTING DEVICE WITH FOLDED INTERPOSER
- Publication number 20070023905
- Publication date Feb 1, 2007
- Intel Corporation
- Iwen Chao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTING DEVICE WITH FOLDED INTERPOSER
- Publication number 20070026569
- Publication date Feb 1, 2007
- Intel Corporation
- Iwen Chao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconducting device with stacked dice
- Publication number 20050224943
- Publication date Oct 13, 2005
- Scott R. Sahaida
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconducting device with folded interposer
- Publication number 20050212112
- Publication date Sep 29, 2005
- Intel Corporation
- Iwen Chao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with low resistive path barrier
- Publication number 20050179111
- Publication date Aug 18, 2005
- Iwen Chao
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Error corrected pre-read for upper page write in a multi-level cell...

Lower page read for multi-level cell memory

Dynamically compensating for degradation of a non-volatile memory d...

Lower page read for multi-level cell memory

Method and apparatus for improving endurance of flash memories

Method of manufacturing semiconducting device with stacked dice

Semiconducting device with folded interposer

Semiconducting device with folded interposer

Semiconducting device with stacked dice

Semiconducting device with folded interposer

Patents Applicationslast 30 patents

DYNAMICALLY COMPENSATING FOR DEGRADATION OF A NON-VOLATILE MEMORY D...

LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY

LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY

ERROR CORRECTED PRE-READ FOR UPPER PAGE WRITE IN A MULTI-LEVEL CELL...

METHOD, APPARATUS AND SYSTEM FOR DETERMINING ACCESS TO A MEMORY ARRAY

METHOD AND APPARATUS FOR IMPROVING ENDURANCE OF FLASH MEMORIES

Semiconducting device with stacked dice

SEMICONDUCTING DEVICE WITH FOLDED INTERPOSER

SEMICONDUCTING DEVICE WITH FOLDED INTERPOSER

Semiconducting device with stacked dice

Semiconducting device with folded interposer

Semiconductor device with low resistive path barrier