Iyengar Srinivasan

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Round Rock, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Analog/digital partitioning of circuit designs for simulation
- Patent number 8,640,073
- Issue date Jan 28, 2014
- Cadence Design Systems, Inc.
- Chandrashekar L. Chetput
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analog/digital partitioning of circuit designs for simulation
- Patent number 8,448,116
- Issue date May 21, 2013
- Cadence Design Systems, Inc.
- Chandrashekar L. Chetput
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for verifying connectivity of electrical circuit components
- Patent number 7,979,262
- Issue date Jul 12, 2011
- Cadence Design Systems, Inc.
- Srinivasan Iyengar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analog/digital partitioning of circuit designs for simulation
- Patent number 7,797,659
- Issue date Sep 14, 2010
- Cadence Design Systems, Inc.
- Chandrashekar L. Chetput
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ANALOG/DIGITAL PARTITIONING OF CIRCUIT DESIGNS FOR SIMULATION
- Publication number 20130326440
- Publication date Dec 5, 2013
- Cadence Design Systems, Inc.
- Chandrashekar L. Chetput
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANALOG/DIGITAL PARTITIONING OF CIRCUIT DESIGNS FOR SIMULATION
- Publication number 20100333050
- Publication date Dec 30, 2010
- Cadence Design Systems, Inc.
- Chandrashekar L. Chetput
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Analog/digital partitioning of circuit designs for simulation
- Publication number 20080184181
- Publication date Jul 31, 2008
- Cadence Design Systems, Inc.
- Chandrashekar L. Chetput
- G06 - COMPUTING CALCULATING COUNTING