Jacky Seiller

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Veurey-Voroize, FR

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Patents Grantslast 30 patents

Information Patent Grant
Method for fabricating electrical bonding pads on a wafer
- Patent number 8,227,332
- Issue date Jul 24, 2012
- STMicroelectronics (Grenoble) SAS
- Romain Coffy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for fabricating electrical bonding pads on a wafer
- Patent number 8,148,258
- Issue date Apr 3, 2012
- STMicroelectronics (Grenoble) SAS
- Romain Coffy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Forming of the last metallization level of an integrated circuit
- Patent number 7,919,864
- Issue date Apr 5, 2011
- STMicroelectronics S.A.
- Jacky Seiller
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR FABRICATING ELECTRICAL BONDING PADS ON A WAFER
- Publication number 20110151657
- Publication date Jun 23, 2011
- STMicroelectronics (Grenoble) SAS
- Romain Coffy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD FOR FABRICATING ELECTRICAL BONDING PADS ON A WAFER
- Publication number 20090134514
- Publication date May 28, 2009
- STMicroelectronics (Grenoble) SAS
- Romain Coffy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED ELECTRONIC CIRCUIT CHIP COMPRISING AN INDUCTOR
- Publication number 20080157273
- Publication date Jul 3, 2008
- STMicroelectronics S.A.
- Jean-Christophe Giraudin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming of the last metallization level of an integrated circuit
- Publication number 20050077626
- Publication date Apr 14, 2005
- Jacky Seiller
- H01 - BASIC ELECTRIC ELEMENTS