Jacson Liu

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Hsin-Chu Hsien, TW

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Patents Grantslast 30 patents

Information Patent Grant
Shallow trench isolation method for a semiconductor wafer
- Patent number 7,045,435
- Issue date May 16, 2006
- Mosel Vitelic Inc.
- Jacson Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of simultaneously implementing differential gate oxide thick...
- Patent number 6,784,115
- Issue date Aug 31, 2004
- Mosel Vitelic, Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene process
- Patent number 6,346,474
- Issue date Feb 12, 2002
- Mosel Viteli Inc.
- Jacson Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating VLSI devices having trench isolation regions
- Patent number 6,319,795
- Issue date Nov 20, 2001
- Mosel Vitelic Inc.
- Jacson Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming self-aligned contact of semiconductor device
- Patent number 6,218,275
- Issue date Apr 17, 2001
- Mosel Vitelic, Inc.
- Jing-Xian Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation method of a semiconductor wafer
- Patent number 6,218,267
- Issue date Apr 17, 2001
- Mosel Vitelic Inc.
- Jacson Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming self-aligned contact hole
- Patent number 6,146,997
- Issue date Nov 14, 2000
- Mosel Vitelic, Inc.
- Jacson Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Shallow Trench Isolation Method for a Semiconductor Wafer
- Publication number 20050191822
- Publication date Sep 1, 2005
- Jacson Liu
- H01 - BASIC ELECTRIC ELEMENTS