Jae-Joon Kim

Person

Yorktown Heights, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Pulsed-latch based razor with 1-cycle error recovery scheme
- Patent number 9,715,437
- Issue date Jul 25, 2017
- International Business Machines Corporation
- Jae-Joon Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulsed-latch based razor with 1-cycle error recovery scheme
- Patent number 9,292,390
- Issue date Mar 22, 2016
- International Business Machines Corporation
- Jae-Joon Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing performance degradation in backup semiconductor chips
- Patent number 9,110,777
- Issue date Aug 18, 2015
- International Business Machines Corporation
- Aditya Bansal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Power napping technique for accelerated negative bias temperature i...
- Patent number 9,086,865
- Issue date Jul 21, 2015
- International Business Machines Corporation
- Aditya Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Usage-based temporal degradation estimation for memory elements
- Patent number 9,064,071
- Issue date Jun 23, 2015
- International Business Machines Corporation
- Aditya Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Usage-based temporal degradation estimation for memory elements
- Patent number 9,058,448
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Aditya Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Estimating delay deterioration due to device degradation in integra...
- Patent number 8,966,420
- Issue date Feb 24, 2015
- International Business Machines Corporation
- Aditya Bansal
- G01 - MEASURING TESTING
Information Patent Grant
AC supply noise reduction in a 3D stack with voltage sensing and cl...
- Patent number 8,587,357
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Jae-Joon Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D chip stack skew reduction with resonant clock and inductive coup...
- Patent number 8,576,000
- Issue date Nov 5, 2013
- International Business Machines Corporation
- Jae-Joon Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Enhanced static random access memory stability using asymmetric acc...
- Patent number 8,526,219
- Issue date Sep 3, 2013
- International Business Machines Corporation
- Aditya Bansal
- G11 - INFORMATION STORAGE
Information Patent Grant
3D chip stack skew reduction with resonant clock and inductive coup...
- Patent number 8,466,739
- Issue date Jun 18, 2013
- International Business Machines Corporation
- Jae-Joon Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Monitoring negative bias temperature instability (NBTI) and/or posi...
- Patent number 8,456,247
- Issue date Jun 4, 2013
- International Business Machines Corporation
- Jae-Joon Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Enhanced static random access memory stability using asymmetric acc...
- Patent number 8,139,400
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Aditya Bansal
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for characterizing device variation in electronic memory ci...
- Patent number 8,086,917
- Issue date Dec 27, 2011
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic circuit for measurement of transistor variability and th...
- Patent number 8,004,305
- Issue date Aug 23, 2011
- International Business Machines Corporation
- Keith A. Jenkins
- G01 - MEASURING TESTING
Information Patent Grant
Asymmetrical memory cells and memories using the cells
- Patent number 7,903,450
- Issue date Mar 8, 2011
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Independent-gate controlled asymmetrical memory cell and memory usi...
- Patent number 7,787,285
- Issue date Aug 31, 2010
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of operating an electronic circuit for measurement of trans...
- Patent number 7,764,080
- Issue date Jul 27, 2010
- International Business Machines Corporation
- Keith A. Jenkins
- G01 - MEASURING TESTING
Information Patent Grant
Memory circuit with decoupled read and write bit lines and improved...
- Patent number 7,746,709
- Issue date Jun 29, 2010
- International Business Machines Corporation
- Rajiv V. Joshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Computer-readable medium encoding a back-gate controlled asymmetric...
- Patent number 7,742,327
- Issue date Jun 22, 2010
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and methods for characterizing device variation in electro...
- Patent number 7,673,195
- Issue date Mar 2, 2010
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuits with reduced leakage power and design structures fo...
- Patent number 7,668,035
- Issue date Feb 23, 2010
- International Business Machines Corporation
- Sam Gat-Shang Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
System to transfer a template transfer body between a motion stage...
- Patent number 7,665,981
- Issue date Feb 23, 2010
- Molecular Imprints, Inc.
- Philip D. Schumaker
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Circuits and design structures for monitoring NBTI (negative bias t...
- Patent number 7,642,864
- Issue date Jan 5, 2010
- International Business Machines Corporation
- Ching-Te K. Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for determining the slew rate of a signal prod...
- Patent number 7,548,822
- Issue date Jun 16, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- G01 - MEASURING TESTING
Information Patent Grant
Techniques for improving write stability of memory with decoupled r...
- Patent number 7,495,969
- Issue date Feb 24, 2009
- International Business Machines Corporation
- Rajiv V. Joshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Computer-readable medium encoding a memory using a back-gate contro...
- Patent number 7,492,628
- Issue date Feb 17, 2009
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic circuit for measurement of transistor variability and th...
- Patent number 7,439,755
- Issue date Oct 21, 2008
- International Business Machines Corporation
- Keith A. Jenkins
- G01 - MEASURING TESTING
Information Patent Grant
Independent-gate controlled asymmetrical memory cell and memory usi...
- Patent number 7,417,889
- Issue date Aug 26, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Asymmetrical memory cells and memories using the cells
- Patent number 7,362,606
- Issue date Apr 22, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
PULSED-LATCH BASED RAZOR WITH 1-CYCLE ERROR RECOVERY SCHEME
- Publication number 20160140005
- Publication date May 19, 2016
- International Business Machines Corporation
- Jae-Joon Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRA...
- Publication number 20150154331
- Publication date Jun 4, 2015
- International Business Machines Corporation
- Aditya Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSED-LATCH BASED RAZOR WITH 1-CYCLE ERROR RECOVERY SCHEME
- Publication number 20140372797
- Publication date Dec 18, 2014
- Jae-Joon Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER NAPPING TECHNIQUE FOR ACCELERATED NEGATIVE BIAS TEMPERATURE I...
- Publication number 20140013131
- Publication date Jan 9, 2014
- International Business Machines Corporation
- Aditya Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-CELL MTJ STRUCTURE WITH INDIVIDUAL ACCESS AND LOGICAL COMBINAT...
- Publication number 20130258750
- Publication date Oct 3, 2013
- International Business Machines Corporation
- JAE-JOON KIM
- G11 - INFORMATION STORAGE
Information Patent Application
ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRA...
- Publication number 20130253868
- Publication date Sep 26, 2013
- International Business Machines Corporation
- Aditya Bansal
- G01 - MEASURING TESTING
Information Patent Application
ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRA...
- Publication number 20130254731
- Publication date Sep 26, 2013
- International Business Machines Corporation
- Aditya Bansal
- G01 - MEASURING TESTING
Information Patent Application
REDUCING PERFORMANCE DEGRADATION IN BACKUP SEMICONDUCTOR CHIPS
- Publication number 20130212414
- Publication date Aug 15, 2013
- International Business Machines Corporation
- Aditya Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USAGE-BASED TEMPORAL DEGRADATION ESTIMATION FOR MEMORY ELEMENTS
- Publication number 20130138407
- Publication date May 30, 2013
- International Business Machines Corporation
- Aditya Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USAGE-BASED TEMPORAL DEGRADATION ESTIMATION FOR MEMORY ELEMENTS
- Publication number 20130138403
- Publication date May 30, 2013
- International Business Machines Corporation
- Aditya Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-Chip Delay Measurement Through a Transistor Array
- Publication number 20130049791
- Publication date Feb 28, 2013
- International Business Machines Corporation
- Keith A. Jenkins
- G01 - MEASURING TESTING
Information Patent Application
AC SUPPLY NOISE REDUCTION IN A 3D STACK WITH VOLTAGE SENSING AND CL...
- Publication number 20130049828
- Publication date Feb 28, 2013
- International Business Machines Corporation
- JAE-JOON KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUP...
- Publication number 20130049824
- Publication date Feb 28, 2013
- International Business Machines Corporation
- JAE-JOON KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUP...
- Publication number 20130049826
- Publication date Feb 28, 2013
- International Business Machines Corporation
- JAE-JOON KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MONITORING NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) AND/OR POSI...
- Publication number 20120182079
- Publication date Jul 19, 2012
- International Business Machines Corporation
- Jae-Joon Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced Static Random Access Memory Stability Using Asymmetric Acc...
- Publication number 20120185817
- Publication date Jul 19, 2012
- International Business Machines Corporation
- Aditya Bansal
- G11 - INFORMATION STORAGE
Information Patent Application
On-Chip Delay Measurement Through a Transistor Array
- Publication number 20120081141
- Publication date Apr 5, 2012
- International Business Machines Corporation
- Keith A. Jenkins
- G01 - MEASURING TESTING
Information Patent Application
METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CI...
- Publication number 20090310430
- Publication date Dec 17, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND TH...
- Publication number 20090309625
- Publication date Dec 17, 2009
- International Business Machines Corporation
- Keith A. Jenkins
- G01 - MEASURING TESTING
Information Patent Application
MEMORY CIRCUITS WITH REDUCED LEAKAGE POWER AND DESIGN STRUCTURES FO...
- Publication number 20090251974
- Publication date Oct 8, 2009
- International Business Machines Corporation
- Sam Gat-Shang Chu
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS T...
- Publication number 20090189703
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM...
- Publication number 20090190426
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACC...
- Publication number 20090185409
- Publication date Jul 23, 2009
- International Business Machines Corporation
- Aditya Bansal
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Circuit with Decoupled Read and Write Bit Lines and Improved...
- Publication number 20090147592
- Publication date Jun 11, 2009
- International Business Machines Corporation
- Rajiv V. Joshi
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRO...
- Publication number 20090091346
- Publication date Apr 9, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRIC...
- Publication number 20090067223
- Publication date Mar 12, 2009
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PROD...
- Publication number 20090018787
- Publication date Jan 15, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods of Operating an Electronic Circuit for Measurement of Trans...
- Publication number 20080315907
- Publication date Dec 25, 2008
- International Business Machines Corporation
- Keith A. Jenkins
- G01 - MEASURING TESTING
Information Patent Application
INDEPENDENT-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USI...
- Publication number 20080278992
- Publication date Nov 13, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques For Improving Write Stability Of Memory With Decoupled R...
- Publication number 20080181029
- Publication date Jul 31, 2008
- International Business Machines Corporation
- Rajiv V. Joshi
- G11 - INFORMATION STORAGE

Jae-Joon Kim

Person

Patents Grantslast 30 patents

Pulsed-latch based razor with 1-cycle error recovery scheme

Pulsed-latch based razor with 1-cycle error recovery scheme

Reducing performance degradation in backup semiconductor chips

Power napping technique for accelerated negative bias temperature i...

Usage-based temporal degradation estimation for memory elements

Usage-based temporal degradation estimation for memory elements

Estimating delay deterioration due to device degradation in integra...

AC supply noise reduction in a 3D stack with voltage sensing and cl...

3D chip stack skew reduction with resonant clock and inductive coup...

Enhanced static random access memory stability using asymmetric acc...

3D chip stack skew reduction with resonant clock and inductive coup...

Monitoring negative bias temperature instability (NBTI) and/or posi...

Enhanced static random access memory stability using asymmetric acc...

Methods for characterizing device variation in electronic memory ci...

Electronic circuit for measurement of transistor variability and th...

Asymmetrical memory cells and memories using the cells

Independent-gate controlled asymmetrical memory cell and memory usi...

Methods of operating an electronic circuit for measurement of trans...

Memory circuit with decoupled read and write bit lines and improved...

Computer-readable medium encoding a back-gate controlled asymmetric...

Circuits and methods for characterizing device variation in electro...

Memory circuits with reduced leakage power and design structures fo...

System to transfer a template transfer body between a motion stage...

Circuits and design structures for monitoring NBTI (negative bias t...

Apparatus and method for determining the slew rate of a signal prod...

Techniques for improving write stability of memory with decoupled r...

Computer-readable medium encoding a memory using a back-gate contro...

Electronic circuit for measurement of transistor variability and th...

Independent-gate controlled asymmetrical memory cell and memory usi...

Asymmetrical memory cells and memories using the cells

Patents Applicationslast 30 patents

PULSED-LATCH BASED RAZOR WITH 1-CYCLE ERROR RECOVERY SCHEME

ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRA...

PULSED-LATCH BASED RAZOR WITH 1-CYCLE ERROR RECOVERY SCHEME

POWER NAPPING TECHNIQUE FOR ACCELERATED NEGATIVE BIAS TEMPERATURE I...

DUAL-CELL MTJ STRUCTURE WITH INDIVIDUAL ACCESS AND LOGICAL COMBINAT...

ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRA...

ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRA...

REDUCING PERFORMANCE DEGRADATION IN BACKUP SEMICONDUCTOR CHIPS

USAGE-BASED TEMPORAL DEGRADATION ESTIMATION FOR MEMORY ELEMENTS

USAGE-BASED TEMPORAL DEGRADATION ESTIMATION FOR MEMORY ELEMENTS

On-Chip Delay Measurement Through a Transistor Array

AC SUPPLY NOISE REDUCTION IN A 3D STACK WITH VOLTAGE SENSING AND CL...

3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUP...

3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUP...

MONITORING NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) AND/OR POSI...

Enhanced Static Random Access Memory Stability Using Asymmetric Acc...

On-Chip Delay Measurement Through a Transistor Array

METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CI...

ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND TH...

MEMORY CIRCUITS WITH REDUCED LEAKAGE POWER AND DESIGN STRUCTURES FO...

CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS T...

CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM...

ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACC...

Memory Circuit with Decoupled Read and Write Bit Lines and Improved...

CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRO...

COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRIC...

APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PROD...

Methods of Operating an Electronic Circuit for Measurement of Trans...

INDEPENDENT-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USI...

Techniques For Improving Write Stability Of Memory With Decoupled R...