Jaesik Lee

Person

San Jose, CA, US

People

Patents Applicationslast 30 patents

Information Patent Application
HIGH-DENSITY SYSTEM-ON-CHIP PARTITIONING
- Publication number 20240332252
- Publication date Oct 3, 2024
- Meta Platforms Technologies, LLC
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D INTEGRATED IN-PACKAGE MAIN MEMORY
- Publication number 20240332275
- Publication date Oct 3, 2024
- Meta Platforms Technologies, LLC
- Jaesik Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D CHIPLET INTEGRATION USING FAN-OUT WAFER-LEVEL PACKAGING
- Publication number 20240274587
- Publication date Aug 15, 2024
- Meta Platforms Technologies, LLC
- Rajendra D. Pendse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Socket To Support High Performance Multi-die ASICs
- Publication number 20240096859
- Publication date Mar 21, 2024
- Google LLC
- Nam Hoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D High Bandwidth Memory and Optical Connectivity Stacking
- Publication number 20240036278
- Publication date Feb 1, 2024
- Google LLC
- Horia Alexandru Toma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Active Silicon D2D Bridge
- Publication number 20230411297
- Publication date Dec 21, 2023
- Google LLC
- Georgios Konstadinidis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Optical Communication for Memory Disaggregation in High Performance...
- Publication number 20230343768
- Publication date Oct 26, 2023
- Google LLC
- Horia Alexandru Toma
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Applicationslast 30 patents

HIGH-DENSITY SYSTEM-ON-CHIP PARTITIONING

3D INTEGRATED IN-PACKAGE MAIN MEMORY

3D CHIPLET INTEGRATION USING FAN-OUT WAFER-LEVEL PACKAGING

Socket To Support High Performance Multi-die ASICs

3D High Bandwidth Memory and Optical Connectivity Stacking

Active Silicon D2D Bridge

Optical Communication for Memory Disaggregation in High Performance...