Jaeyong Park

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple dual bit memory integrated circuit system
- Patent number 7,692,236
- Issue date Apr 6, 2010
- Spansion LLC
- Michael Brennan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SONOS memory with inversion bit-lines
- Patent number 7,501,677
- Issue date Mar 10, 2009
- Spansion LLC
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Grant
Recessed channel with separated ONO memory device
- Patent number 7,394,125
- Issue date Jul 1, 2008
- FASL LLC
- Jaeyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for gate formation in a semiconductor device
- Patent number 7,320,914
- Issue date Jan 22, 2008
- Spansion LLC
- Hajime Wada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for gate formation in a semiconductor device
- Patent number 7,220,643
- Issue date May 22, 2007
- Spansion LLC
- Hajime Wada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Aluminum oxide as liner or cover layer to spacers in memory device
- Patent number 7,196,008
- Issue date Mar 27, 2007
- Spansion LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SONOS memory with inversion bit-lines
- Patent number 7,151,293
- Issue date Dec 19, 2006
- Spansion, LLC
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Grant
Recessed channel with separated ONO memory device
- Patent number 7,067,377
- Issue date Jun 27, 2006
- FASL LLC
- Jaeyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming wordlines having irregular spacing in a memory a...
- Patent number 7,052,961
- Issue date May 30, 2006
- Spansion LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ONO fabrication process for increasing oxygen content at bottom oxi...
- Patent number 7,033,957
- Issue date Apr 25, 2006
- FASL, LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...
- Patent number 7,018,896
- Issue date Mar 28, 2006
- Advanced Micro Devices, Inc.
- Minh V. Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Disposable hard mask for memory bitline scaling
- Patent number 7,018,868
- Issue date Mar 28, 2006
- Advanced Micro Devices, Inc.
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ONO fabrication process for reducing oxygen vacancy content in bott...
- Patent number 6,969,886
- Issue date Nov 29, 2005
- Fasl, LLC
- Jaeyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory device and method of fabrication thereof including a b...
- Patent number 6,958,511
- Issue date Oct 25, 2005
- Fasl, LLC
- Arvind Halliyal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of formation of semiconductor resistant to hot carrier injec...
- Patent number 6,949,433
- Issue date Sep 27, 2005
- FASL LLC
- Shiraiwa Hidehiko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bitline hard mask spacer flow for memory cell scaling
- Patent number 6,927,145
- Issue date Aug 9, 2005
- Advanced Micro Devices, Inc.
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for preventing UV radiation damage in a memory...
- Patent number 6,894,342
- Issue date May 17, 2005
- Spansion LLC
- Angela Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a planar structure charge trapping memory cel...
- Patent number 6,855,608
- Issue date Feb 15, 2005
- Advanced Micro Devices, Inc.
- Mark Ramsbey
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and method for preventing process-induced UV radiation da...
- Patent number 6,833,581
- Issue date Dec 21, 2004
- Spansion LLC
- Angela Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ONO fabrication process for reducing oxygen vacancy content in bott...
- Patent number 6,803,275
- Issue date Oct 12, 2004
- Fasl, LLC
- Jaeyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...
- Patent number 6,774,432
- Issue date Aug 10, 2004
- Advanced Micro Devices, Inc.
- Minh V. Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for preventing UV radiation damage and increas...
- Patent number 6,765,254
- Issue date Jul 20, 2004
- Advanced Micro Devices, Inc.
- Angela Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for reducing hydrogen contamination in dielectric materials...
- Patent number 6,740,605
- Issue date May 25, 2004
- Advanced Micro Devices, Inc.
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SONOS memory with inversion bit-lines
- Publication number 20070058442
- Publication date Mar 15, 2007
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Application
UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...
- Publication number 20040191989
- Publication date Sep 30, 2004
- Minh V. Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BI...
- Publication number 20040151025
- Publication date Aug 5, 2004
- Minh V. Ngo
- H01 - BASIC ELECTRIC ELEMENTS

Jaeyong Park

Person

Patents Grantslast 30 patents

Multiple dual bit memory integrated circuit system

SONOS memory with inversion bit-lines

Recessed channel with separated ONO memory device

System and method for gate formation in a semiconductor device

System and method for gate formation in a semiconductor device

Aluminum oxide as liner or cover layer to spacers in memory device

SONOS memory with inversion bit-lines

Recessed channel with separated ONO memory device

Method for forming wordlines having irregular spacing in a memory a...

ONO fabrication process for increasing oxygen content at bottom oxi...

UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...

Disposable hard mask for memory bitline scaling

ONO fabrication process for reducing oxygen vacancy content in bott...

Flash memory device and method of fabrication thereof including a b...

Method of formation of semiconductor resistant to hot carrier injec...

Bitline hard mask spacer flow for memory cell scaling

Structure and method for preventing UV radiation damage in a memory...

Method of fabricating a planar structure charge trapping memory cel...

Structure and method for preventing process-induced UV radiation da...

ONO fabrication process for reducing oxygen vacancy content in bott...

UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...

Structure and method for preventing UV radiation damage and increas...

Process for reducing hydrogen contamination in dielectric materials...

Patents Applicationslast 30 patents

SONOS memory with inversion bit-lines

UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...

UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BI...