Jagdeep Bal

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and methods for automatic time measurements
- Patent number 11,079,723
- Issue date Aug 3, 2021
- Integrated Device Technology, Inc.
- Min Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Wirelessly synchronized clock networks
- Patent number 10,687,293
- Issue date Jun 16, 2020
- Integrated Device Technology, Inc.
- Jagdeep Bal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Wirelessly synchronized clock networks
- Patent number 10,264,542
- Issue date Apr 16, 2019
- Integrated Device Technology, Inc.
- Jagdeep Bal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Separate clock synchronous architecture
- Patent number 10,261,539
- Issue date Apr 16, 2019
- Integrated Device Technology, Inc.
- Jagdeep Bal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for deskewing output clock signals
- Patent number 9,614,508
- Issue date Apr 4, 2017
- Integrated Device Technology, Inc.
- Jagdeep Bal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual mode clock using a common resonator and associated method of use
- Patent number 9,581,973
- Issue date Feb 28, 2017
- Integrated Device Technology, Inc.
- Pankaj Goyal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Crystal-less jitter attenuator
- Patent number 9,553,570
- Issue date Jan 24, 2017
- Integrated Device Technology, Inc.
- Jagdeep Bal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and systems for analog-to-digital conversion (ADC) using an...
- Patent number 9,553,602
- Issue date Jan 24, 2017
- Integrated Device Technology, Inc.
- I-chang Wu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fractional reference-injection PLL
- Patent number 9,369,139
- Issue date Jun 14, 2016
- Integrated Device Technology, Inc.
- Min Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-spurious fractional N-frequency divider and method of use
- Patent number 9,362,928
- Issue date Jun 7, 2016
- Integrated Device Technology, Inc.
- Pankaj Goyal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock distribution systems for low power applications
- Patent number 8,854,086
- Issue date Oct 7, 2014
- Integrated Device Technology, Inc.
- Jagdeep Bal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Spread spectrum clock generation technique for imaging applications
- Patent number 8,164,367
- Issue date Apr 24, 2012
- Integrated Device Technology, Inc.
- Jagdeep Bal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock circuit with harmonic frequency detector
- Patent number 7,786,763
- Issue date Aug 31, 2010
- Integrated Device Technology, Inc.
- Jagdeep Bal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for a hybrid phase lock loop frequency synthes...
- Patent number 7,180,377
- Issue date Feb 20, 2007
- Silicon Clocks Inc.
- Colin Wai Mun Leong
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Hybrid analog/digital phase lock loop frequency synthesizer
- Patent number 7,084,709
- Issue date Aug 1, 2006
- Colin Wai Mun Leong
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHODS FOR AUTOMATIC TIME MEASUREMENTS
- Publication number 20190243312
- Publication date Aug 8, 2019
- Integrated Device Technology, Inc.
- Min Chu
- G04 - HOROLOGY
Information Patent Application
WIRELESSLY SYNCHRONIZED CLOCK NETWORKS
- Publication number 20190223128
- Publication date Jul 18, 2019
- Integrated Device Technology, Inc.
- Jagdeep Bal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
WIRELESSLY SYNCHRONIZED CLOCK NETWORKS
- Publication number 20180288718
- Publication date Oct 4, 2018
- Integrated Device Technology, Inc.
- Jagdeep Bal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SEPARATE CLOCK SYNCHRONOUS ARCHITECTURE
- Publication number 20180284835
- Publication date Oct 4, 2018
- Integrated Device Technology, Inc.
- Jagdeep Bal
- G06 - COMPUTING CALCULATING COUNTING

Jagdeep Bal

Person

Patents Grantslast 30 patents

Apparatus and methods for automatic time measurements

Wirelessly synchronized clock networks

Wirelessly synchronized clock networks

Separate clock synchronous architecture

System and method for deskewing output clock signals

Dual mode clock using a common resonator and associated method of use

Crystal-less jitter attenuator

Methods and systems for analog-to-digital conversion (ADC) using an...

Fractional reference-injection PLL

Low-spurious fractional N-frequency divider and method of use

Clock distribution systems for low power applications

Spread spectrum clock generation technique for imaging applications

Clock circuit with harmonic frequency detector

Method and apparatus for a hybrid phase lock loop frequency synthes...

Hybrid analog/digital phase lock loop frequency synthesizer

Patents Applicationslast 30 patents

APPARATUS AND METHODS FOR AUTOMATIC TIME MEASUREMENTS

WIRELESSLY SYNCHRONIZED CLOCK NETWORKS

WIRELESSLY SYNCHRONIZED CLOCK NETWORKS

SEPARATE CLOCK SYNCHRONOUS ARCHITECTURE