Jagdish Pathak

Person

Los Alstos Hills, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory row line driver circuit
- Patent number 6,487,139
- Issue date Nov 26, 2002
- Jagdish Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference cell for high speed sensing in non-volatile memories
- Patent number 6,411,549
- Issue date Jun 25, 2002
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero power power-on reset circuit
- Patent number 5,936,444
- Issue date Aug 10, 1999
- Atmel Corporation
- Jagdish Pathak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor memory having a current balancing circuit
- Patent number 5,917,754
- Issue date Jun 29, 1999
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having a power supply-independent low power consumpti...
- Patent number 5,828,603
- Issue date Oct 27, 1998
- Atmel Corporation
- Jagdish Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero power fuse circuit
- Patent number 5,731,734
- Issue date Mar 24, 1998
- Atmel Corporation
- Jagdish Pathak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for programming flash EEPROM devices
- Patent number 5,621,738
- Issue date Apr 15, 1997
- Eastman Kodak Company
- John Caywood
- G11 - INFORMATION STORAGE
Information Patent Grant
Sector erasable flash EEPROM
- Patent number 5,270,980
- Issue date Dec 14, 1993
- Eastman Kodak Company
- Jagdish Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture of high speed synchronous state machine
- Patent number 5,023,484
- Issue date Jun 11, 1991
- Cypress Semiconductor Corporation
- Jagdish Pathak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual I/O macrocell for high speed synchronous state machine
- Patent number 4,879,481
- Issue date Nov 7, 1989
- Cypress Semiconductor Corporation
- Jagdish Pathak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power sense amplifier for programmable logic device
- Patent number 4,851,720
- Issue date Jul 25, 1989
- Cypress Semiconductor Corporation
- Jagdish Pathak
- G05 - CONTROLLING REGULATING

Jagdish Pathak

Person

Patents Grantslast 30 patents

Memory row line driver circuit

Reference cell for high speed sensing in non-volatile memories

Zero power power-on reset circuit

Semiconductor memory having a current balancing circuit

Memory device having a power supply-independent low power consumpti...

Zero power fuse circuit

Method for programming flash EEPROM devices

Sector erasable flash EEPROM

Architecture of high speed synchronous state machine

Dual I/O macrocell for high speed synchronous state machine

Low power sense amplifier for programmable logic device