Jagjot Kaur

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Milpitas, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for optimizing scan pipelining in hierarchical...
- Patent number 11,409,931
- Issue date Aug 9, 2022
- Cadence Design Systems, Inc.
- Jagjot Kaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Devices and methods for test point insertion coverage
- Patent number 10,740,515
- Issue date Aug 11, 2020
- Cadence Design Systems, Inc.
- Jagjot Kaur
- G01 - MEASURING TESTING
Information Patent Grant
Power and scan resource reduction in integrated circuit designs hav...
- Patent number 10,417,363
- Issue date Sep 17, 2019
- Cadence Design Systems, Inc.
- Jagjot Kaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing core wrappers in an integrated circuit
- Patent number 10,234,504
- Issue date Mar 19, 2019
- Cadence Design Systems, Inc.
- Subhasish Mukherjee
- G01 - MEASURING TESTING