Jama I. Barreh

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit for fast interrupt handling
- Patent number 11,507,414
- Issue date Nov 22, 2022
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache diagnostic techniques
- Patent number 11,023,342
- Issue date Jun 1, 2021
- Western Digital Technologies, Inc.
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threaded instruction buffer design
- Patent number 10,860,326
- Issue date Dec 8, 2020
- Oracle International Corporation
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threaded instruction buffer design
- Patent number 10,346,173
- Issue date Jul 9, 2019
- Oracle International Corporation
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Miss buffer for a multi-threaded processor
- Patent number 9,529,594
- Issue date Dec 27, 2016
- Oracle International Corporation
- Manish K. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Perceptron-based branch prediction mechanism for predicting conditi...
- Patent number 8,904,156
- Issue date Dec 2, 2014
- Oracle America, Inc.
- Manish K. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and method providing instruction support for instructions...
- Patent number 8,555,038
- Issue date Oct 8, 2013
- Oracle International Corporation
- Christopher H. Olson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor operating mode for mitigating dependency conditions betwe...
- Patent number 8,504,805
- Issue date Aug 6, 2013
- Oracle America, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic tag allocation in a multithreaded out-of-order processor
- Patent number 8,429,386
- Issue date Apr 23, 2013
- Oracle America, Inc.
- Paul J. Jordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logical map table for detecting dependency conditions between instr...
- Patent number 8,335,912
- Issue date Dec 18, 2012
- Oracle America, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid instruction buffer
- Patent number 8,225,034
- Issue date Jul 17, 2012
- Oracle America, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arbitrating cache misses in a multithreaded/multi-core processor
- Patent number 8,037,250
- Issue date Oct 11, 2011
- Oracle America, Inc.
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay slot handling in a processor
- Patent number 7,861,063
- Issue date Dec 28, 2010
- Oracle America, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling duplicate cache misses in a multithreaded/multi-core proce...
- Patent number 7,434,000
- Issue date Oct 7, 2008
- Sun Microsystems, Inc.
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent bypass to instruction buffers in a fine grain multithrea...
- Patent number 7,383,403
- Issue date Jun 3, 2008
- Sun Microsystems, Inc.
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache error handling in a multithreaded/multi-core processor
- Patent number 7,353,445
- Issue date Apr 1, 2008
- Sun Microsystems, Inc.
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimal address state in a fine grain multithreaded processor
- Patent number 7,343,474
- Issue date Mar 11, 2008
- Sun Microsystems, Inc.
- Paul J. Jordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fetch speculation in a multithreaded processor
- Patent number 7,185,178
- Issue date Feb 27, 2007
- Sun Microsystems, Inc.
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Circuit for Fast Interrupt Handling
- Publication number 20220164220
- Publication date May 26, 2022
- Western Digital Technologies, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction Error Handling
- Publication number 20220164254
- Publication date May 26, 2022
- Western Digital Technologies, Inc.
- Matthew B. Smittle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE DIAGNOSTIC TECHNIQUES
- Publication number 20200174903
- Publication date Jun 4, 2020
- Western Digital Technologies, Inc.
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-THREADED INSTRUCTION BUFFER DESIGN
- Publication number 20200004549
- Publication date Jan 2, 2020
- ORACLE INTERNATIONAL CORPORATION
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER INSTRUCTION BUFFER FOR HIGH PERFORMANCE PROCESSORS
- Publication number 20160055001
- Publication date Feb 25, 2016
- Gideon Levinsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORING A TARGET ADDRESS OF A CONTROL TRANSFER INSTRUCTION IN AN IN...
- Publication number 20130138888
- Publication date May 30, 2013
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-THREADED INSTRUCTION BUFFER DESIGN
- Publication number 20120233441
- Publication date Sep 13, 2012
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MISS BUFFER FOR A MULTI-THREADED PROCESSOR
- Publication number 20120137077
- Publication date May 31, 2012
- Manish K. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR AND METHOD PROVIDING INSTRUCTION SUPPORT FOR INSTRUCTIONS...
- Publication number 20110296142
- Publication date Dec 1, 2011
- Christopher H. Olson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERCEPTRON-BASED BRANCH PREDICTION MECHANISM FOR PREDICTING CONDITI...
- Publication number 20110087866
- Publication date Apr 14, 2011
- Manish K. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC TAG ALLOCATION IN A MULTITHREADED OUT-OF-ORDER PROCESSOR
- Publication number 20100333098
- Publication date Dec 30, 2010
- Paul J. Jordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHYSICALLY-INDEXED LOGICAL MAP TABLE
- Publication number 20100274961
- Publication date Oct 28, 2010
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGICAL MAP TABLE FOR DETECTING DEPENDENCY CONDITIONS
- Publication number 20100274993
- Publication date Oct 28, 2010
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR OPERATING MODE FOR MITIGATING DEPENDENCY CONDITIONS
- Publication number 20100274994
- Publication date Oct 28, 2010
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING

Jama I. Barreh

Person

Patents Grantslast 30 patents

Circuit for fast interrupt handling

Cache diagnostic techniques

Multi-threaded instruction buffer design

Multi-threaded instruction buffer design

Miss buffer for a multi-threaded processor

Perceptron-based branch prediction mechanism for predicting conditi...

Processor and method providing instruction support for instructions...

Processor operating mode for mitigating dependency conditions betwe...

Dynamic tag allocation in a multithreaded out-of-order processor

Logical map table for detecting dependency conditions between instr...

Hybrid instruction buffer

Arbitrating cache misses in a multithreaded/multi-core processor

Delay slot handling in a processor

Handling duplicate cache misses in a multithreaded/multi-core proce...

Concurrent bypass to instruction buffers in a fine grain multithrea...

Cache error handling in a multithreaded/multi-core processor

Minimal address state in a fine grain multithreaded processor

Fetch speculation in a multithreaded processor

Patents Applicationslast 30 patents

Circuit for Fast Interrupt Handling

Instruction Error Handling

CACHE DIAGNOSTIC TECHNIQUES

MULTI-THREADED INSTRUCTION BUFFER DESIGN

LOW POWER INSTRUCTION BUFFER FOR HIGH PERFORMANCE PROCESSORS

STORING A TARGET ADDRESS OF A CONTROL TRANSFER INSTRUCTION IN AN IN...

MULTI-THREADED INSTRUCTION BUFFER DESIGN

MISS BUFFER FOR A MULTI-THREADED PROCESSOR

PROCESSOR AND METHOD PROVIDING INSTRUCTION SUPPORT FOR INSTRUCTIONS...

PERCEPTRON-BASED BRANCH PREDICTION MECHANISM FOR PREDICTING CONDITI...

DYNAMIC TAG ALLOCATION IN A MULTITHREADED OUT-OF-ORDER PROCESSOR

PHYSICALLY-INDEXED LOGICAL MAP TABLE

LOGICAL MAP TABLE FOR DETECTING DEPENDENCY CONDITIONS

PROCESSOR OPERATING MODE FOR MITIGATING DEPENDENCY CONDITIONS