James Andrew Garrard Seawright

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Mountain View, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Clock model for formal verification of a digital circuit description
- Patent number 8,060,847
- Issue date Nov 15, 2011
- Mentor Graphics Corporation
- James Andrew Garrard Seawright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock model for formal verification of a digital circuit description
- Patent number 7,487,483
- Issue date Feb 3, 2009
- James Andrew Garrard Seawright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selection of initial states for formal verification
- Patent number 7,454,324
- Issue date Nov 18, 2008
- James Andrew Garrard Seawright
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CLOCK MODEL FOR FORMAL VERIFICATION OF A DIGITAL CIRCUIT DESCRIPTION
- Publication number 20090144684
- Publication date Jun 4, 2009
- Mentor Graphics Corp.
- James Andrew Garrard Seawright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock model for formal verification of a digital circuit description
- Publication number 20070271536
- Publication date Nov 22, 2007
- Mentor Graphics Corp.
- James Andrew Garrard Seawright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR OPTIMIZED PARTITIONING OF FINITE STATE MAC...
- Publication number 20020023256
- Publication date Feb 21, 2002
- JAMES ANDREW GARRARD SEAWRIGHT
- G06 - COMPUTING CALCULATING COUNTING