James Brian Johnson

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory with parallel main and test interfaces
- Patent number 12,243,610
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-purpose signaling for a memory system
- Patent number 11,893,245
- Issue date Feb 6, 2024
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock locking for packet based communications of memory devices
- Patent number 11,837,318
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency offset for frame-based communications
- Patent number 11,797,186
- Issue date Oct 24, 2023
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable memory architectures
- Patent number 11,614,875
- Issue date Mar 28, 2023
- Micron Technology, Inc.
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frame protocol of memory device
- Patent number 11,580,049
- Issue date Feb 14, 2023
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-purpose signaling for a memory system
- Patent number 11,392,299
- Issue date Jul 19, 2022
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock locking for packet based communications of memory devices
- Patent number 11,373,691
- Issue date Jun 28, 2022
- Micron Technology Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frame protocol of memory device
- Patent number 11,226,920
- Issue date Jan 18, 2022
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable memory architectures
- Patent number 10,936,221
- Issue date Mar 2, 2021
- Micron Technology, Inc.
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frame protocol of memory device
- Patent number 10,579,578
- Issue date Mar 3, 2020
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory systems and methods for controlling the timing of receiving...
- Patent number 9,411,538
- Issue date Aug 9, 2016
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and method using stacked memory device dice, and syst...
- Patent number 9,275,698
- Issue date Mar 1, 2016
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits, devices, systems, and methods of operation for capturing...
- Patent number 9,129,662
- Issue date Sep 8, 2015
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Sharing resources in multi-dice stacks
- Patent number 8,977,809
- Issue date Mar 10, 2015
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-timed error correcting code evaluation system and method
- Patent number 8,930,786
- Issue date Jan 6, 2015
- Micron Technology, Inc.
- James B. Johnson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory system and method using stacked memory device dice, and syst...
- Patent number 8,793,460
- Issue date Jul 29, 2014
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory systems and methods for controlling the timing of receiving...
- Patent number 8,751,754
- Issue date Jun 10, 2014
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits, devices, systems, and methods of operation for capturing...
- Patent number 8,687,434
- Issue date Apr 1, 2014
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-timed error correcting code evaluation system and method
- Patent number 8,555,127
- Issue date Oct 8, 2013
- Micron Technology, Inc.
- James B. Johnson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory system and method using stacked memory device dice, and syst...
- Patent number 8,533,416
- Issue date Sep 10, 2013
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory systems and methods for controlling the timing of receiving...
- Patent number 8,521,979
- Issue date Aug 27, 2013
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Strobe apparatus, systems, and methods
- Patent number 8,406,071
- Issue date Mar 26, 2013
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-timed error correcting code evaluation system and method
- Patent number 8,347,165
- Issue date Jan 1, 2013
- Micron Technology, Inc.
- James Brian Johnson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuits, devices, systems, and methods of operation for capturing...
- Patent number 8,284,617
- Issue date Oct 9, 2012
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Strobe apparatus, systems, and methods
- Patent number 8,169,841
- Issue date May 1, 2012
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits, devices, systems, and methods of operation for capturing...
- Patent number 8,154,931
- Issue date Apr 10, 2012
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for capturing data signals using a data strobe si...
- Patent number 8,040,753
- Issue date Oct 18, 2011
- Micron Technology, Inc.
- Joo S. Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and method using stacked memory device dice, and syst...
- Patent number 8,010,866
- Issue date Aug 30, 2011
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Write latency tracking using a delay lock loop in a synchronous DRAM
- Patent number 7,881,149
- Issue date Feb 1, 2011
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
PROCESSING IN MEMORY REGISTERS
- Publication number 20250069629
- Publication date Feb 27, 2025
- Micron Technology, Inc.
- Dmitri Yudanov
- G11 - INFORMATION STORAGE
Information Patent Application
ROW HAMMER MITIGATION FOR STACKED MEMORY ARCHITECTURES
- Publication number 20250045388
- Publication date Feb 6, 2025
- Micron Technology, Inc.
- Nathan A. Eckel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROW HAMMER MITIGATION RELIABILITY IN STACKED MEMORY ARCHITECTURES
- Publication number 20250045389
- Publication date Feb 6, 2025
- Micron Technology, Inc.
- Chun-Yi Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INFORMATION BROADCAST TECHNIQUES FOR STACKED MEMORY ARCHITECTURES
- Publication number 20240403165
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Nathan A. Eckel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE TECHNIQUES FOR STACKED MEMORY ARCHITECTURES
- Publication number 20240404581
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Ameen D. Akel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DATA PATH SIGNAL AMPLIFICATION IN COUPLED SEMICONDUCTOR SYSTEMS
- Publication number 20240355371
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSISTOR ARCHITECTURES IN COUPLED SEMICONDUCTOR SYSTEMS
- Publication number 20240313098
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- James Brian Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR MODULAR DIE CONFIGURATIONS FOR MULTI-CHANNEL MEMORY
- Publication number 20240237363
- Publication date Jul 11, 2024
- Micron Technology, Inc.
- James Brian Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REPAIR TECHNIQUES FOR COUPLED MEMORY DIES
- Publication number 20240194287
- Publication date Jun 13, 2024
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR THERMAL DISTRIBUTION IN COUPLED SEMICONDUCTOR SYSTEMS
- Publication number 20240186274
- Publication date Jun 6, 2024
- Micron Technology, Inc.
- Amy Rae Griffin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR COUPLED HOST AND MEMORY DIES
- Publication number 20240176523
- Publication date May 30, 2024
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH PARALLEL MAIN AND TEST INTERFACES
- Publication number 20240071556
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL ROUTING STRUCTURES INCLUDING A PLURALITY OF PARALLEL CONDUCT...
- Publication number 20230268351
- Publication date Aug 24, 2023
- Micron Technology, Inc.
- Kunal R. Parekh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-PURPOSE SIGNALING FOR A MEMORY SYSTEM
- Publication number 20220404985
- Publication date Dec 22, 2022
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK LOCKING FOR PACKET BASED COMMUNICATIONS OF MEMORY DEVICES
- Publication number 20220374039
- Publication date Nov 24, 2022
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FRAME PROTOCOL OF MEMORY DEVICE
- Publication number 20220121609
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATENCY OFFSET FOR FRAME-BASED COMMUNICATIONS
- Publication number 20210191622
- Publication date Jun 24, 2021
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PURPOSE SIGNALING FOR A MEMORY SYSTEM
- Publication number 20210191627
- Publication date Jun 24, 2021
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK LOCKING FOR PACKET BASED COMMUNICATIONS OF MEMORY DEVICES
- Publication number 20210193198
- Publication date Jun 24, 2021
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE MEMORY ARCHITECTURES
- Publication number 20210124512
- Publication date Apr 29, 2021
- Micron Technology, Inc.
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FRAME PROTOCOL OF MEMORY DEVICE
- Publication number 20200159687
- Publication date May 21, 2020
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE MEMORY ARCHITECTURES
- Publication number 20190121560
- Publication date Apr 25, 2019
- Micron Technology, Inc.
- Brent Keeth
- G11 - INFORMATION STORAGE
Information Patent Application
FRAME PROTOCOL OF MEMORY DEVICE
- Publication number 20190121775
- Publication date Apr 25, 2019
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING RESOURCES IN MULTI-DICE STACKS
- Publication number 20150179240
- Publication date Jun 25, 2015
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...
- Publication number 20140337570
- Publication date Nov 13, 2014
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING...
- Publication number 20140258666
- Publication date Sep 11, 2014
- Micron Technology, Inc.
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR CAPTURING...
- Publication number 20140204685
- Publication date Jul 24, 2014
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-TIMED ERROR CORRECTING CODE EVALUATION SYSTEM AND METHOD
- Publication number 20140040696
- Publication date Feb 6, 2014
- Micron Technology, Inc.
- James B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...
- Publication number 20130346722
- Publication date Dec 26, 2013
- Micron Technology, Inc.
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING...
- Publication number 20130318298
- Publication date Nov 28, 2013
- Micron Technology, Inc.
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING

James Brian Johnson

Person

Patents Grantslast 30 patents

Memory with parallel main and test interfaces

Multi-purpose signaling for a memory system

Clock locking for packet based communications of memory devices

Latency offset for frame-based communications

Reconfigurable memory architectures

Frame protocol of memory device

Multi-purpose signaling for a memory system

Clock locking for packet based communications of memory devices

Frame protocol of memory device

Reconfigurable memory architectures

Frame protocol of memory device

Memory systems and methods for controlling the timing of receiving...

Memory system and method using stacked memory device dice, and syst...

Circuits, devices, systems, and methods of operation for capturing...

Sharing resources in multi-dice stacks

Self-timed error correcting code evaluation system and method

Memory system and method using stacked memory device dice, and syst...

Memory systems and methods for controlling the timing of receiving...

Circuits, devices, systems, and methods of operation for capturing...

Self-timed error correcting code evaluation system and method

Memory system and method using stacked memory device dice, and syst...

Memory systems and methods for controlling the timing of receiving...

Strobe apparatus, systems, and methods

Self-timed error correcting code evaluation system and method

Circuits, devices, systems, and methods of operation for capturing...

Strobe apparatus, systems, and methods

Circuits, devices, systems, and methods of operation for capturing...

System and method for capturing data signals using a data strobe si...

Memory system and method using stacked memory device dice, and syst...

Write latency tracking using a delay lock loop in a synchronous DRAM

Patents Applicationslast 30 patents

PROCESSING IN MEMORY REGISTERS

ROW HAMMER MITIGATION FOR STACKED MEMORY ARCHITECTURES

ROW HAMMER MITIGATION RELIABILITY IN STACKED MEMORY ARCHITECTURES

INFORMATION BROADCAST TECHNIQUES FOR STACKED MEMORY ARCHITECTURES

INTERFACE TECHNIQUES FOR STACKED MEMORY ARCHITECTURES

DATA PATH SIGNAL AMPLIFICATION IN COUPLED SEMICONDUCTOR SYSTEMS

TRANSISTOR ARCHITECTURES IN COUPLED SEMICONDUCTOR SYSTEMS

TECHNIQUES FOR MODULAR DIE CONFIGURATIONS FOR MULTI-CHANNEL MEMORY

REPAIR TECHNIQUES FOR COUPLED MEMORY DIES

TECHNIQUES FOR THERMAL DISTRIBUTION IN COUPLED SEMICONDUCTOR SYSTEMS

TECHNIQUES FOR COUPLED HOST AND MEMORY DIES

MEMORY WITH PARALLEL MAIN AND TEST INTERFACES

SIGNAL ROUTING STRUCTURES INCLUDING A PLURALITY OF PARALLEL CONDUCT...

MULTI-PURPOSE SIGNALING FOR A MEMORY SYSTEM

CLOCK LOCKING FOR PACKET BASED COMMUNICATIONS OF MEMORY DEVICES

FRAME PROTOCOL OF MEMORY DEVICE

LATENCY OFFSET FOR FRAME-BASED COMMUNICATIONS

MULTI-PURPOSE SIGNALING FOR A MEMORY SYSTEM

CLOCK LOCKING FOR PACKET BASED COMMUNICATIONS OF MEMORY DEVICES

RECONFIGURABLE MEMORY ARCHITECTURES

FRAME PROTOCOL OF MEMORY DEVICE

RECONFIGURABLE MEMORY ARCHITECTURES

FRAME PROTOCOL OF MEMORY DEVICE

SHARING RESOURCES IN MULTI-DICE STACKS

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...

MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING...

CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR CAPTURING...

SELF-TIMED ERROR CORRECTING CODE EVALUATION SYSTEM AND METHOD

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...

MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING...