James C. Parker

Person

Upper Milford Township, Lehigh County, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods for designing integrated circuits employing voltage scaling...
- Patent number 8,806,408
- Issue date Aug 12, 2014
- Agere Systems Inc.
- James C. Parker
- G01 - MEASURING TESTING
Information Patent Grant
System and method for employing signoff-quality timing analysis inf...
- Patent number 8,713,506
- Issue date Apr 29, 2014
- LSI Corporation
- Bruce Zahn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for designing integrated circuits employing pre-determined...
- Patent number 8,689,161
- Issue date Apr 1, 2014
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical design flow generator
- Patent number 8,683,407
- Issue date Mar 25, 2014
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling approach for timing closure in hierarchical designs levera...
- Patent number 8,543,951
- Issue date Sep 24, 2013
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for designing integrated circuits employing a partitioned hi...
- Patent number 8,539,419
- Issue date Sep 17, 2013
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systematic benchmarking system and method for standardized data cre...
- Patent number 8,539,423
- Issue date Sep 17, 2013
- Agere Systems, LLC
- Joseph J. Jamann
- G01 - MEASURING TESTING
Information Patent Grant
Modeling approach for timing closure in hierarchical designs levera...
- Patent number 8,341,573
- Issue date Dec 25, 2012
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systematic benchmarking system and method for standardized data cre...
- Patent number 8,307,324
- Issue date Nov 6, 2012
- Agere Systems LLC
- Joseph J. Jamann
- G01 - MEASURING TESTING
Information Patent Grant
Systematic, normalized metric for analyzing and comparing optimizat...
- Patent number 8,281,266
- Issue date Oct 2, 2012
- Agere Systems LLC
- Joseph J. Jamann
- G01 - MEASURING TESTING
Information Patent Grant
Method for designing integrated circuits employing a partitioned hi...
- Patent number 8,239,805
- Issue date Aug 7, 2012
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for designing integrated circuits employing context-sensiti...
- Patent number 8,127,264
- Issue date Feb 28, 2012
- LSI Corporation
- James C. Parker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Establishing benchmarks for analyzing benefits associated with volt...
- Patent number 8,122,422
- Issue date Feb 21, 2012
- LSI Corporation
- Vishwas M. Rao
- G01 - MEASURING TESTING
Information Patent Grant
Systematic benchmarking system and method for standardized data cre...
- Patent number 8,024,694
- Issue date Sep 20, 2011
- Agere Systems Inc.
- Joseph J. Jamann
- G01 - MEASURING TESTING
Information Patent Grant
Modifying integrated circuit designs to achieve multiple operating...
- Patent number 7,930,674
- Issue date Apr 19, 2011
- Agere Systems Inc.
- James C. Parker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area-efficient power switching cell
- Patent number 7,712,066
- Issue date May 4, 2010
- Agere Systems, INC
- Martin J. Gasper, Jr.
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING...
- Publication number 20140298277
- Publication date Oct 2, 2014
- James C. Parker
- G01 - MEASURING TESTING
Information Patent Application
MULTI-CHIP MODULE CONNECTION BY WAY OF BRIDGING BLOCKS
- Publication number 20140131854
- Publication date May 15, 2014
- LSI Corporation
- Donald E. Hawk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CORRECT-BY-CONST...
- Publication number 20140059505
- Publication date Feb 27, 2014
- LSI Corporation
- Gerard M. Blair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL DESIGN FLOW GENERATOR
- Publication number 20130339912
- Publication date Dec 19, 2013
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CRE...
- Publication number 20130104096
- Publication date Apr 25, 2013
- AGERE SYSTEMS LLC
- Joseph J. Jamann
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZA...
- Publication number 20130055175
- Publication date Feb 28, 2013
- Joseph J. Jamann
- G01 - MEASURING TESTING
Information Patent Application
NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS...
- Publication number 20130036393
- Publication date Feb 7, 2013
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INF...
- Publication number 20120221995
- Publication date Aug 30, 2012
- Bruce Zahn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HI...
- Publication number 20120174048
- Publication date Jul 5, 2012
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS...
- Publication number 20120095746
- Publication date Apr 19, 2012
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING PRE-DETERMINED...
- Publication number 20120011484
- Publication date Jan 12, 2012
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CRE...
- Publication number 20110307852
- Publication date Dec 15, 2011
- Agere Systems, Inc.
- Joseph J. Jamann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ESTABLISHING BENCHMARKS FOR ANALYZING BENEFITS ASSOCIATED WITH VOLT...
- Publication number 20110023004
- Publication date Jan 27, 2011
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITI...
- Publication number 20110022996
- Publication date Jan 27, 2011
- James C. Parker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HI...
- Publication number 20110022998
- Publication date Jan 27, 2011
- LSI Corporation
- Vishwas M. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZAT...
- Publication number 20100037188
- Publication date Feb 11, 2010
- Agere Systems, Inc.
- Joseph J. Jamann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING...
- Publication number 20100026378
- Publication date Feb 4, 2010
- Agere Systems, Inc.
- James C. Parker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CRE...
- Publication number 20090281772
- Publication date Nov 12, 2009
- Agere Systems, Inc.
- Joseph J. Jamann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modifying Integrated Circuit Designs to Achieve Multiple Operating...
- Publication number 20080244473
- Publication date Oct 2, 2008
- James C. Parker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Area-efficient power switching cell
- Publication number 20070164806
- Publication date Jul 19, 2007
- Martin J. Gasper
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated circuit having second substrate to facilitate core power...
- Publication number 20070164446
- Publication date Jul 19, 2007
- Donald E. Hawk
- H01 - BASIC ELECTRIC ELEMENTS

James C. Parker

Person

Patents Grantslast 30 patents

Methods for designing integrated circuits employing voltage scaling...

System and method for employing signoff-quality timing analysis inf...

Methods for designing integrated circuits employing pre-determined...

Hierarchical design flow generator

Modeling approach for timing closure in hierarchical designs levera...

Method for designing integrated circuits employing a partitioned hi...

Systematic benchmarking system and method for standardized data cre...

Modeling approach for timing closure in hierarchical designs levera...

Systematic benchmarking system and method for standardized data cre...

Systematic, normalized metric for analyzing and comparing optimizat...

Method for designing integrated circuits employing a partitioned hi...

Methods for designing integrated circuits employing context-sensiti...

Establishing benchmarks for analyzing benefits associated with volt...

Systematic benchmarking system and method for standardized data cre...

Modifying integrated circuit designs to achieve multiple operating...

Area-efficient power switching cell

Patents Applicationslast 30 patents

METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING...

MULTI-CHIP MODULE CONNECTION BY WAY OF BRIDGING BLOCKS

METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CORRECT-BY-CONST...

HIERARCHICAL DESIGN FLOW GENERATOR

SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CRE...

SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZA...

NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS...

SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INF...

METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HI...

NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS...

METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING PRE-DETERMINED...

SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CRE...

ESTABLISHING BENCHMARKS FOR ANALYZING BENEFITS ASSOCIATED WITH VOLT...

METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITI...

METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HI...

SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZAT...

METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING...

SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CRE...

Modifying Integrated Circuit Designs to Achieve Multiple Operating...

Area-efficient power switching cell

Integrated circuit having second substrate to facilitate core power...