JAMES D. BURNETT

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and structures for multiport memory devices
- Patent number 9,455,260
- Issue date Sep 27, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Perry H. Pelley
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device with single-event latch-up prevention circuitry
- Patent number 9,123,545
- Issue date Sep 1, 2015
- Jianan Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM bit cell with reduced bit line pre-charge voltage
- Patent number 9,111,638
- Issue date Aug 18, 2015
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and structures for multiport memory devices
- Patent number 9,111,634
- Issue date Aug 18, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Perry H. Pelley
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line driver circuits and methods for SRAM bit cell with reduce...
- Patent number 8,947,970
- Issue date Feb 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Perry H. Pelley
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for reduced coupling between digital signal lines
- Patent number 8,836,371
- Issue date Sep 16, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Perry H. Pelley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for sensing on-chip characteristics
- Patent number 8,766,703
- Issue date Jul 1, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Jianan Yang
- G05 - CONTROLLING REGULATING
Information Patent Grant
Single event latch-up prevention techniques for a semiconductor device
- Patent number 8,685,800
- Issue date Apr 1, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Jianan Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory having a latching sense amplifier resistant to negative bias...
- Patent number 8,659,322
- Issue date Feb 25, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Alexander B. Hoefler
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple device types including an inverted-T channel transistor an...
- Patent number 8,643,066
- Issue date Feb 4, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Byoung L. Min
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors with immersed contacts
- Patent number 8,633,515
- Issue date Jan 21, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for testing a memory embedded in an integrated circuit
- Patent number 8,531,899
- Issue date Sep 10, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Shayan Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having an embedded memory and method for testing...
- Patent number 8,379,466
- Issue date Feb 19, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Shayan Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Transistors with immersed contacts
- Patent number 8,314,448
- Issue date Nov 20, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage-based memory size scaling in a data processing system
- Patent number 8,156,357
- Issue date Apr 10, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Shayan Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit using FinFETs and having a static random access...
- Patent number 8,088,657
- Issue date Jan 3, 2012
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single transistor memory cell with reduced recombination rates
- Patent number 7,986,006
- Issue date Jul 26, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with immersed contacts and methods of forming thereof
- Patent number 7,968,394
- Issue date Jun 28, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming an electronic device including a fin-type trans...
- Patent number 7,939,412
- Issue date May 10, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an integrated circuit
- Patent number 7,824,988
- Issue date Nov 2, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Alexander Hoefler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with asymmetry for data storage circuitry
- Patent number 7,799,644
- Issue date Sep 21, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory having self-timed bit line boost circuit and method therefor
- Patent number 7,800,959
- Issue date Sep 21, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Lawrence F. Childs
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit using FinFETs and having a static random access...
- Patent number 7,754,560
- Issue date Jul 13, 2010
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit and method for optimizing memory sense amplifier timing
- Patent number 7,733,711
- Issue date Jun 8, 2010
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic device including a fin-type transistor structure and a p...
- Patent number 7,723,805
- Issue date May 25, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interlayer dielectric under stress for an integrated circuit
- Patent number 7,718,485
- Issue date May 18, 2010
- Freescale Semiconductor, Inc,
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming an electronic device including a fin-type struc...
- Patent number 7,709,303
- Issue date May 4, 2010
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory system with RAM array and redundant RAM memory cells having...
- Patent number 7,684,264
- Issue date Mar 23, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Bradford L. Hunter
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cells with lower power consumption during a write operation
- Patent number 7,609,541
- Issue date Oct 27, 2009
- FREESCALE SEMICONDUCTOR, INC.
- James David Burnett
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a memory with low voltage read/write oper...
- Patent number 7,542,369
- Issue date Jun 2, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Prashant U. Kenkare
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND STRUCTURES FOR MULTIPORT MEMORY DEVICES
- Publication number 20150357338
- Publication date Dec 10, 2015
- FREESCALE SEMICONDUCTOR, INC.
- PERRY H. PELLEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Systems And Methods For Reduced Coupling Between Digital Signal Lines
- Publication number 20140203841
- Publication date Jul 24, 2014
- Perry H. Pelley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE WITH SINGLE-EVENT LATCH-UP PREVENTION CIRCUITRY
- Publication number 20140167102
- Publication date Jun 19, 2014
- FREESCALE SEMICONDUCTOR, INC.
- JIANAN YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE-EVENT LATCH-UP PREVENTION TECHNIQUES FOR A SEMICONDUCTOR DEVICE
- Publication number 20140027810
- Publication date Jan 30, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Jianan Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SRAM BIT CELL WITH REDUCED BIT LINE PRE-CHARGE VOLTAGE
- Publication number 20140016402
- Publication date Jan 16, 2014
- JAMES D. BURNETT
- G11 - INFORMATION STORAGE
Information Patent Application
WORD LINE DRIVER CIRCUITS AND METHODS FOR SRAM BIT CELL WITH REDUCE...
- Publication number 20140016400
- Publication date Jan 16, 2014
- PERRY H. PELLEY
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND STRUCTURES FOR MULTIPORT MEMORY DEVICES
- Publication number 20140015061
- Publication date Jan 16, 2014
- PERRY H. PELLEY
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS FOR TESTING A MEMORY EMBEDDED IN AN INTEGRATED CIRCUIT
- Publication number 20130019133
- Publication date Jan 17, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Shayan Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSISTORS WITH IMMERSED CONTACTS
- Publication number 20130009222
- Publication date Jan 10, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. ORLOWSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY HAVING A LATCHING SENSE AMPLIFIER RESISTANT TO NEGATIVE BIAS...
- Publication number 20120194222
- Publication date Aug 2, 2012
- Alexander B. Hoefler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRANSISTORS WITH IMMERSED CONTACTS
- Publication number 20110210395
- Publication date Sep 1, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. ORLOWSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT HAVING AN EMBEDDED MEMORY AND METHOD FOR TESTING...
- Publication number 20100246297
- Publication date Sep 30, 2010
- Shayan Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT USING FINFETS AND HAVING A STATIC RANDOM ACCESS...
- Publication number 20100230762
- Publication date Sep 16, 2010
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VOLTAGE-BASED MEMORY SIZE SCALING IN A DATA PROCESSING SYSTEM
- Publication number 20100191990
- Publication date Jul 29, 2010
- Shayan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DEVICE INCLUDING A FIN-TYPE TRANSISTOR STRUCTURE AND A P...
- Publication number 20100190308
- Publication date Jul 29, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. ORLOWSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT
- Publication number 20100190354
- Publication date Jul 29, 2010
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING AN INTEGRATED CIRCUIT
- Publication number 20100181629
- Publication date Jul 22, 2010
- Alexander Hoefler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY HAVING SELF-TIMED BIT LINE BOOST CIRCUIT AND METHOD THEREFOR
- Publication number 20100074032
- Publication date Mar 25, 2010
- Lawrence F. Childs
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD FOR OPTIMIZING MEMORY SENSE AMPLIFIER TIMING
- Publication number 20100061162
- Publication date Mar 11, 2010
- James D. Burnett
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE TRANSISTOR MEMORY CELL WITH REDUCED RECOMBINATION RATES
- Publication number 20090166700
- Publication date Jul 2, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. ORLOWSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE DEVICE TYPES INCLUDING AN INVERTED-T CHANNEL TRANSISTOR AN...
- Publication number 20090039418
- Publication date Feb 12, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Byoung W. Min
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY SYSTEM WITH REDUNDANT RAM MEMORY CELLS HAVING A DIFFERENT DE...
- Publication number 20080181034
- Publication date Jul 31, 2008
- Bradford L. Hunter
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELLS WITH LOWER POWER CONSUMPTION DURING A WRITE OPERATION
- Publication number 20080158938
- Publication date Jul 3, 2008
- James David Burnett
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE HAVING A P-MOS TRANSISTOR WITH SOURCE-DRAIN EX...
- Publication number 20080090359
- Publication date Apr 17, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Sinan Goktepeli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH ASYMMETRY FOR DATA STORAGE CIRCUITRY
- Publication number 20080026529
- Publication date Jan 31, 2008
- Ted R. White
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT HAVING A MEMORY WITH LOW VOLTAGE READ/WRITE OPER...
- Publication number 20080019206
- Publication date Jan 24, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Prashant U. Kenkare
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and method for adjusting an operating parameter of an int...
- Publication number 20070220388
- Publication date Sep 20, 2007
- Qadeer A. Quereshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT
- Publication number 20070218618
- Publication date Sep 20, 2007
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and method for operating a memory circuit
- Publication number 20070211517
- Publication date Sep 13, 2007
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- G11 - INFORMATION STORAGE
Information Patent Application
Switch device and method
- Publication number 20070211526
- Publication date Sep 13, 2007
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- G11 - INFORMATION STORAGE

JAMES D. BURNETT

Person

Patents Grantslast 30 patents

Methods and structures for multiport memory devices

Semiconductor device with single-event latch-up prevention circuitry

SRAM bit cell with reduced bit line pre-charge voltage

Methods and structures for multiport memory devices

Word line driver circuits and methods for SRAM bit cell with reduce...

Systems and methods for reduced coupling between digital signal lines

Method and apparatus for sensing on-chip characteristics

Single event latch-up prevention techniques for a semiconductor device

Memory having a latching sense amplifier resistant to negative bias...

Multiple device types including an inverted-T channel transistor an...

Transistors with immersed contacts

Methods for testing a memory embedded in an integrated circuit

Integrated circuit having an embedded memory and method for testing...

Transistors with immersed contacts

Voltage-based memory size scaling in a data processing system

Integrated circuit using FinFETs and having a static random access...

Single transistor memory cell with reduced recombination rates

Transistor with immersed contacts and methods of forming thereof

Process for forming an electronic device including a fin-type trans...

Method of forming an integrated circuit

Transistor with asymmetry for data storage circuitry

Memory having self-timed bit line boost circuit and method therefor

Integrated circuit using FinFETs and having a static random access...

Circuit and method for optimizing memory sense amplifier timing

Electronic device including a fin-type transistor structure and a p...

Interlayer dielectric under stress for an integrated circuit

Process for forming an electronic device including a fin-type struc...

Memory system with RAM array and redundant RAM memory cells having...

Memory cells with lower power consumption during a write operation

Integrated circuit having a memory with low voltage read/write oper...

Patents Applicationslast 30 patents

METHODS AND STRUCTURES FOR MULTIPORT MEMORY DEVICES

Systems And Methods For Reduced Coupling Between Digital Signal Lines

SEMICONDUCTOR DEVICE WITH SINGLE-EVENT LATCH-UP PREVENTION CIRCUITRY

SINGLE-EVENT LATCH-UP PREVENTION TECHNIQUES FOR A SEMICONDUCTOR DEVICE

SRAM BIT CELL WITH REDUCED BIT LINE PRE-CHARGE VOLTAGE

WORD LINE DRIVER CIRCUITS AND METHODS FOR SRAM BIT CELL WITH REDUCE...

METHODS AND STRUCTURES FOR MULTIPORT MEMORY DEVICES

METHODS FOR TESTING A MEMORY EMBEDDED IN AN INTEGRATED CIRCUIT

TRANSISTORS WITH IMMERSED CONTACTS

MEMORY HAVING A LATCHING SENSE AMPLIFIER RESISTANT TO NEGATIVE BIAS...

TRANSISTORS WITH IMMERSED CONTACTS

INTEGRATED CIRCUIT HAVING AN EMBEDDED MEMORY AND METHOD FOR TESTING...

INTEGRATED CIRCUIT USING FINFETS AND HAVING A STATIC RANDOM ACCESS...

VOLTAGE-BASED MEMORY SIZE SCALING IN A DATA PROCESSING SYSTEM

ELECTRONIC DEVICE INCLUDING A FIN-TYPE TRANSISTOR STRUCTURE AND A P...

INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT

METHOD OF FORMING AN INTEGRATED CIRCUIT

MEMORY HAVING SELF-TIMED BIT LINE BOOST CIRCUIT AND METHOD THEREFOR

CIRCUIT AND METHOD FOR OPTIMIZING MEMORY SENSE AMPLIFIER TIMING

SINGLE TRANSISTOR MEMORY CELL WITH REDUCED RECOMBINATION RATES

MULTIPLE DEVICE TYPES INCLUDING AN INVERTED-T CHANNEL TRANSISTOR AN...

MEMORY SYSTEM WITH REDUNDANT RAM MEMORY CELLS HAVING A DIFFERENT DE...

MEMORY CELLS WITH LOWER POWER CONSUMPTION DURING A WRITE OPERATION

SEMICONDUCTOR DEVICE HAVING A P-MOS TRANSISTOR WITH SOURCE-DRAIN EX...

TRANSISTOR WITH ASYMMETRY FOR DATA STORAGE CIRCUITRY

INTEGRATED CIRCUIT HAVING A MEMORY WITH LOW VOLTAGE READ/WRITE OPER...

Apparatus and method for adjusting an operating parameter of an int...

INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT

System and method for operating a memory circuit

Switch device and method