James David Sproch

Person

Monte Sereno, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processor instruction dispatch configuration
- Patent number 12,175,287
- Issue date Dec 24, 2024
- Groq, Inc.
- Brian Lee Kurtz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy provisioning
- Patent number 11,960,346
- Issue date Apr 16, 2024
- Groq, Inc.
- James David Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for floating or applying voltage to a well of...
- Patent number 10,741,538
- Issue date Aug 11, 2020
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for floating or applying voltage to a well of...
- Patent number 9,728,528
- Issue date Aug 8, 2017
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for floating or applying voltage to a well of...
- Patent number 9,287,253
- Issue date Mar 15, 2016
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Placing transistors in proximity to through-silicon vias
- Patent number 9,275,182
- Issue date Mar 1, 2016
- Synopsys, Inc.
- James David Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placing transistors in proximity to through-silicon vias
- Patent number 9,003,348
- Issue date Apr 7, 2015
- Synopsys, Inc.
- James David Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ESD/antenna diodes for through-silicon vias
- Patent number 8,999,766
- Issue date Apr 7, 2015
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determination of meta-stable latch bias voltages
- Patent number 8,904,336
- Issue date Dec 2, 2014
- Synopsys, Inc.
- John Henry Pasternak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ESD/antenna diodes for through-silicon vias
- Patent number 8,877,638
- Issue date Nov 4, 2014
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placing transistors in proximity to through-silicon vias
- Patent number 8,661,387
- Issue date Feb 25, 2014
- Synopsys, Inc.
- James David Sproch
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for placing transistors in proximity to throug...
- Patent number 8,362,622
- Issue date Jan 29, 2013
- Synopsys, Inc.
- James David Sproch
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
ESD/antenna diodes for through-silicon vias
- Patent number 8,264,065
- Issue date Sep 11, 2012
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for improved precomputation to minimize power...
- Patent number 6,704,878
- Issue date Mar 9, 2004
- Synopsys, Inc.
- Luca Benini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Path dependent power modeling
- Patent number 6,480,815
- Issue date Nov 12, 2002
- Synopsys, Inc.
- Janet Olson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for pipe stage gating within an operating pipelin...
- Patent number 6,247,134
- Issue date Jun 12, 2001
- Synopsys, Inc.
- James D. Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional power modeling table having dual output capacitan...
- Patent number 6,195,630
- Issue date Feb 27, 2001
- Synopsys, Inc.
- Ashutosh S. Mauskar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for determining a signal that controls the applic...
- Patent number 6,038,381
- Issue date Mar 14, 2000
- Synopsys, Inc.
- Michael Munch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Path dependent power modeling
- Patent number 5,949,689
- Issue date Sep 7, 1999
- Synopsys, Inc.
- Janet Olson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional power modeling table having dual output capacitan...
- Patent number 5,903,476
- Issue date May 11, 1999
- Synopsys, Inc.
- Ashutosh S. Mauskar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State dependent power modeling
- Patent number 5,838,579
- Issue date Nov 17, 1998
- Synopsys, Inc.
- Janet Olson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Chip-to-Chip Flit Rate Synchronization
- Publication number 20240393825
- Publication date Nov 28, 2024
- Groq, Inc.
- James Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTING ATTACKS ON POWER SUPPLIES BY COMPARING TWO SHIFT REGISTERS
- Publication number 20240394418
- Publication date Nov 28, 2024
- Groq, Inc.
- James Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK PERIOD SYNTHESIS
- Publication number 20240385641
- Publication date Nov 21, 2024
- Groq, Inc.
- James David Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Period Synthesis For Fine-grain Power Management
- Publication number 20240385671
- Publication date Nov 21, 2024
- Groq, Inc.
- James David Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENERGY PROVISIONING
- Publication number 20240256027
- Publication date Aug 1, 2024
- Groq, Inc.
- James David Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Management of a Power Regulator in a Processor During High Cu...
- Publication number 20240248524
- Publication date Jul 25, 2024
- Groq, Inc.
- Santosh Raghavan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Preemptive Processor Power Supply Regulator Feedback Modulation to...
- Publication number 20240176406
- Publication date May 30, 2024
- Groq, Inc.
- Vadim Heyfitch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR INSTRUCTION DISPATCH CONFIGURATION
- Publication number 20240118922
- Publication date Apr 11, 2024
- Groq, Inc.
- Brian Lee Kurtz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Floating or Applying Voltage to a Well of...
- Publication number 20170330872
- Publication date Nov 16, 2017
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS
- Publication number 20150205904
- Publication date Jul 23, 2015
- Synopsys, Inc.
- James David Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR FLOATING OR APPLYING VOLTAGE TO A WELL OF...
- Publication number 20150162320
- Publication date Jun 11, 2015
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS
- Publication number 20140173545
- Publication date Jun 19, 2014
- Synopsys, Inc.
- James David Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS
- Publication number 20140109027
- Publication date Apr 17, 2014
- Synopsys, Inc.
- Qing Su Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Placing Transistors In Proximity to Throug...
- Publication number 20130132914
- Publication date May 23, 2013
- James David Sproch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for floating or applying voltage to a well of...
- Publication number 20130113547
- Publication date May 9, 2013
- Synopsys Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP
- Publication number 20130026575
- Publication date Jan 31, 2013
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS
- Publication number 20120295433
- Publication date Nov 22, 2012
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS
- Publication number 20110095367
- Publication date Apr 28, 2011
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PLACING TRANSISTORS IN PROXIMITY TO THROUG...
- Publication number 20100270597
- Publication date Oct 28, 2010
- Synopsys, Inc.
- JAMES DAVID SPROCH
- G06 - COMPUTING CALCULATING COUNTING

James David Sproch

Person

Patents Grantslast 30 patents

Processor instruction dispatch configuration

Energy provisioning

Method and apparatus for floating or applying voltage to a well of...

Method and apparatus for floating or applying voltage to a well of...

Method and apparatus for floating or applying voltage to a well of...

Placing transistors in proximity to through-silicon vias

Placing transistors in proximity to through-silicon vias

ESD/antenna diodes for through-silicon vias

Determination of meta-stable latch bias voltages

ESD/antenna diodes for through-silicon vias

Placing transistors in proximity to through-silicon vias

Method and apparatus for placing transistors in proximity to throug...

ESD/antenna diodes for through-silicon vias

Apparatus and method for improved precomputation to minimize power...

Path dependent power modeling

Method and system for pipe stage gating within an operating pipelin...

Three-dimensional power modeling table having dual output capacitan...

Method and system for determining a signal that controls the applic...

Path dependent power modeling

Three-dimensional power modeling table having dual output capacitan...

State dependent power modeling

Patents Applicationslast 30 patents

Chip-to-Chip Flit Rate Synchronization

DETECTING ATTACKS ON POWER SUPPLIES BY COMPARING TWO SHIFT REGISTERS

CLOCK PERIOD SYNTHESIS

Clock Period Synthesis For Fine-grain Power Management

ENERGY PROVISIONING

Power Management of a Power Regulator in a Processor During High Cu...

Preemptive Processor Power Supply Regulator Feedback Modulation to...

PROCESSOR INSTRUCTION DISPATCH CONFIGURATION

Method and Apparatus for Floating or Applying Voltage to a Well of...

PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS

METHOD AND APPARATUS FOR FLOATING OR APPLYING VOLTAGE TO A WELL OF...

PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS

ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS

Method and Apparatus for Placing Transistors In Proximity to Throug...

Method and apparatus for floating or applying voltage to a well of...

THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP

ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS

ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS

METHOD AND APPARATUS FOR PLACING TRANSISTORS IN PROXIMITY TO THROUG...