James E. Payne

Person

Boulder Creek, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
High speed zero DC power programmable logic device (PLD) architecture
- Patent number 6,809,550
- Issue date Oct 26, 2004
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Power-on reset circuit
- Patent number 6,744,291
- Issue date Jun 1, 2004
- Atmel Corporation
- James E. Payne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High voltage bit/column latch for Vcc operation
- Patent number 6,618,289
- Issue date Sep 9, 2003
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Drive circuit for liquid crystal display cell
- Patent number 6,476,785
- Issue date Nov 5, 2002
- Atmel Corporation
- Saroj Pathak
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Reference cell for high speed sensing in non-volatile memories
- Patent number 6,411,549
- Issue date Jun 25, 2002
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power voltage regulator circuit for use in an integrated circui...
- Patent number 6,320,454
- Issue date Nov 20, 2001
- Atmel Corporation
- Saroj Pathak
- G05 - CONTROLLING REGULATING
Information Patent Grant
Circuit for transferring high voltage video signal without signal loss
- Patent number 6,140,993
- Issue date Oct 31, 2000
- Atmel Corporation
- Saroj Pathak
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Method and apparatus for testing a video display chip
- Patent number 6,115,305
- Issue date Sep 5, 2000
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Fuse circuit having zero power draw for partially blown condition
- Patent number 5,999,038
- Issue date Dec 7, 1999
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with zero power idle mode
- Patent number 5,963,496
- Issue date Oct 5, 1999
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero power high speed configuration memory
- Patent number 5,946,267
- Issue date Aug 31, 1999
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero power power-on reset circuit
- Patent number 5,936,444
- Issue date Aug 10, 1999
- Atmel Corporation
- Jagdish Pathak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bitline load and precharge structure for an SRAM memory
- Patent number 5,781,469
- Issue date Jul 14, 1998
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero power fuse circuit
- Patent number 5,731,734
- Issue date Mar 24, 1998
- Atmel Corporation
- Jagdish Pathak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-speed, non-volatile electrically programmable and erasable cel...
- Patent number 5,680,346
- Issue date Oct 21, 1997
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Breakdown protection circuit using high voltage detection
- Patent number 5,493,244
- Issue date Feb 20, 1996
- Atmel Corporation
- Saroj Pathak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electrostatic discharge circuit for high speed, high voltage circuitry
- Patent number 5,473,500
- Issue date Dec 5, 1995
- Atmel Corporation
- James E. Payne
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Zero power high speed programmable circuit device architecture
- Patent number 5,440,508
- Issue date Aug 8, 1995
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing non-volatile memories
- Patent number 5,383,193
- Issue date Jan 17, 1995
- Atmel Corporation
- Saroj Pathak
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Voltage level shifter circuit having high speed and low switching p...
- Publication number 20040104756
- Publication date Jun 3, 2004
- James E. Payne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low standby power SRAM
- Publication number 20040090820
- Publication date May 13, 2004
- Saroj Pathak
- G11 - INFORMATION STORAGE
Information Patent Application
High speed zero DC power programmable logic device (PLD) architecture
- Publication number 20040056679
- Publication date Mar 25, 2004
- Saroj Pathak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Power-on reset circuit
- Publication number 20040041601
- Publication date Mar 4, 2004
- James E. Payne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High voltage bit/column latch for Vcc operation
- Publication number 20030081448
- Publication date May 1, 2003
- Saroj Pathak
- G11 - INFORMATION STORAGE

James E. Payne

Person

Patents Grantslast 30 patents

High speed zero DC power programmable logic device (PLD) architecture

Power-on reset circuit

High voltage bit/column latch for Vcc operation

Drive circuit for liquid crystal display cell

Reference cell for high speed sensing in non-volatile memories

Low power voltage regulator circuit for use in an integrated circui...

Circuit for transferring high voltage video signal without signal loss

Method and apparatus for testing a video display chip

Fuse circuit having zero power draw for partially blown condition

Sense amplifier with zero power idle mode

Zero power high speed configuration memory

Zero power power-on reset circuit

Bitline load and precharge structure for an SRAM memory

Zero power fuse circuit

High-speed, non-volatile electrically programmable and erasable cel...

Breakdown protection circuit using high voltage detection

Electrostatic discharge circuit for high speed, high voltage circuitry

Zero power high speed programmable circuit device architecture

Method for testing non-volatile memories

Patents Applicationslast 30 patents

Voltage level shifter circuit having high speed and low switching p...

Low standby power SRAM

High speed zero DC power programmable logic device (PLD) architecture

Power-on reset circuit

High voltage bit/column latch for Vcc operation