James E. Vasck

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Austin, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Method of area compaction for integrated circuit layout design
- Patent number 7,904,869
- Issue date Mar 8, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Kathleen C. Yu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF AREA COMPACTION FOR INTEGRATED CIRCUIT LAYOUT DESIGN
- Publication number 20090158229
- Publication date Jun 18, 2009
- Kathleen C. Yu
- G06 - COMPUTING CALCULATING COUNTING