James G. BALLARD

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptive power grid generation
- Patent number 10,185,801
- Issue date Jan 22, 2019
- Oracle International Corporation
- Kiran Kishore Vedantam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mitigating wire capacitance in an integrated circuit
- Patent number 9,910,951
- Issue date Mar 6, 2018
- Oracle International Corporation
- Kiran Vedantam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mitigating electromigration effects using parallel pillars
- Patent number 9,768,111
- Issue date Sep 19, 2017
- Oracle International Corporation
- Mark O'Brien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mitigating electromigration effects using parallel pillars
- Patent number 9,235,674
- Issue date Jan 12, 2016
- Oracle International Corporation
- Mark O'Brien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for flexible and repeatable pre-route generation
- Patent number 8,627,255
- Issue date Jan 7, 2014
- Oracle International Corporation
- Kiran Vedantam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low RC global clock distribution
- Patent number 8,214,790
- Issue date Jul 3, 2012
- Oracle America
- Robert P. Masleid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, computer-readable media and computer-implemented tools for...
- Patent number 8,091,058
- Issue date Jan 3, 2012
- Oracle America, Inc.
- James G. Ballard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing driven pin assignment
- Patent number 7,577,933
- Issue date Aug 18, 2009
- Sun Microsystems, Inc.
- Yi Wu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ADAPTIVE POWER GRID GENERATION
- Publication number 20180203971
- Publication date Jul 19, 2018
- ORACLE INTERNATIONAL CORPORATION
- Kiran Kishore Vedantam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATING WIRE CAPACITANCE IN AN INTEGRATED CIRCUIT
- Publication number 20170053054
- Publication date Feb 23, 2017
- ORACLE INTERNATIONAL CORPORATION
- Kiran VEDANTAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATING ELECTROMIGRATION EFFECTS USING PARALLEL PILLARS
- Publication number 20160086884
- Publication date Mar 24, 2016
- ORACLE INTERNATIONAL CORPORATION
- Mark O'BRIEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MITIGATING ELECTROMIGRATION EFFECTS USING PARALLEL PILLARS
- Publication number 20140252644
- Publication date Sep 11, 2014
- ORACLE INTERNATIONAL CORPORATION
- Mark O'BRIEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR FLEXIBLE AND REPEATABLE PRE-ROUTE GENERATION
- Publication number 20120110537
- Publication date May 3, 2012
- Oracle International Corporation
- Kiran Vedantam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW RC GLOBAL CLOCK DISTRIBUTION
- Publication number 20100229142
- Publication date Sep 9, 2010
- SUN MICROSYSTEMS, INC.
- Robert P. Masleid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CLOCK AND POWER DISTRIBUTION
- Publication number 20100181685
- Publication date Jul 22, 2010
- SUN MICROSYSTEMS, INC.
- Robert P. Masleid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS, COMPUTER-READABLE MEDIA AND COMPUTER-IMPLEMENTED TOOLS FOR...
- Publication number 20100128760
- Publication date May 27, 2010
- SUN MICROSYSTEMS, INC.
- James G. Ballard
- G06 - COMPUTING CALCULATING COUNTING

James G. BALLARD

Person

Patents Grantslast 30 patents

Adaptive power grid generation

Mitigating wire capacitance in an integrated circuit

Mitigating electromigration effects using parallel pillars

Mitigating electromigration effects using parallel pillars

Methods and systems for flexible and repeatable pre-route generation

Low RC global clock distribution

Methods, computer-readable media and computer-implemented tools for...

Timing driven pin assignment

Patents Applicationslast 30 patents

ADAPTIVE POWER GRID GENERATION

MITIGATING WIRE CAPACITANCE IN AN INTEGRATED CIRCUIT

MITIGATING ELECTROMIGRATION EFFECTS USING PARALLEL PILLARS

MITIGATING ELECTROMIGRATION EFFECTS USING PARALLEL PILLARS

METHODS AND SYSTEMS FOR FLEXIBLE AND REPEATABLE PRE-ROUTE GENERATION

LOW RC GLOBAL CLOCK DISTRIBUTION

INTEGRATED CLOCK AND POWER DISTRIBUTION

METHODS, COMPUTER-READABLE MEDIA AND COMPUTER-IMPLEMENTED TOOLS FOR...