James H. Kukula

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for modeling an HDL design using symbolic simulation
- Patent number 8,306,802
- Issue date Nov 6, 2012
- Synopsys, Inc.
- Yunshan Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating a boolean SAT solver into a router
- Patent number 7,904,867
- Issue date Mar 8, 2011
- Synopsys, Inc.
- Jerry R. Burch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase abstraction for formal verification
- Patent number 7,890,894
- Issue date Feb 15, 2011
- Synopsys, Inc.
- Per Bjesse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase abstraction for formal verification
- Patent number 7,343,575
- Issue date Mar 11, 2008
- Synopsys, Inc.
- Per Bjesse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for solving constraints
- Patent number 7,257,786
- Issue date Aug 14, 2007
- Synopsys, Inc.
- James Herbert Kukula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch modeling technique for formal verification
- Patent number 7,254,793
- Issue date Aug 7, 2007
- Synopsys, Inc.
- Yirng-An Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing generator-based verification
- Patent number 7,149,987
- Issue date Dec 12, 2006
- Synopsys, Inc.
- Yunshan Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for solving constraints
- Patent number 7,107,553
- Issue date Sep 12, 2006
- Synopsys, Inc.
- Brian Eugene Lockyear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for formally constraining random simulation
- Patent number 7,092,858
- Issue date Aug 15, 2006
- Synopsys, Inc.
- James Herbert Kukula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for automata-based approach to state reachability...
- Patent number 6,059,837
- Issue date May 9, 2000
- Synopsys, Inc.
- James H. Kukula
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Integrating a boolean SAT solver into a router
- Publication number 20080250376
- Publication date Oct 9, 2008
- Jerry R. Burch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Phase Abstraction For Formal Verification
- Publication number 20080134114
- Publication date Jun 5, 2008
- Synopsys, Inc.
- Per Bjesse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Modeling an HDL Design Using Symbolic Simulation
- Publication number 20080126066
- Publication date May 29, 2008
- Synopsys, Inc.
- Yunshan Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Phase abstraction for formal verification
- Publication number 20060253815
- Publication date Nov 9, 2006
- Synopsys, Inc.
- Per Bjesse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latch modeling technique for formal verification
- Publication number 20060190870
- Publication date Aug 24, 2006
- Synopsys, Inc.
- Yirng-An Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for performing generator-based verification
- Publication number 20050198597
- Publication date Sep 8, 2005
- Yunshan Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for solving constraints
- Publication number 20050044512
- Publication date Feb 24, 2005
- Brian Eugene Lockyear
- G06 - COMPUTING CALCULATING COUNTING

James H. Kukula

Person

Patents Grantslast 30 patents

Method for modeling an HDL design using symbolic simulation

Integrating a boolean SAT solver into a router

Phase abstraction for formal verification

Phase abstraction for formal verification

Method and apparatus for solving constraints

Latch modeling technique for formal verification

Method and apparatus for performing generator-based verification

Method and apparatus for solving constraints

Method and apparatus for formally constraining random simulation

Method and system for automata-based approach to state reachability...

Patents Applicationslast 30 patents

Integrating a boolean SAT solver into a router

Phase Abstraction For Formal Verification

Method for Modeling an HDL Design Using Symbolic Simulation

Phase abstraction for formal verification

Latch modeling technique for formal verification

Method and apparatus for performing generator-based verification

Method and apparatus for solving constraints