James H. P. Wang

Person

Anaheim, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Combined transparent/non-transparent cache
- Patent number 10,776,022
- Issue date Sep 15, 2020
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power saving with dynamic pulse insertion
- Patent number 10,270,434
- Issue date Apr 23, 2019
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined transparent/non-transparent cache
- Patent number 10,241,705
- Issue date Mar 26, 2019
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphical processing unit (GPU) implementing a plurality of virtual...
- Patent number 10,120,728
- Issue date Nov 6, 2018
- Apple Inc.
- Robert A. Drebin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphical processing unit (GPU) implementing a plurality of virtual...
- Patent number 9,727,385
- Issue date Aug 8, 2017
- Apple Inc.
- Robert A. Drebin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-blocking memory management unit
- Patent number 9,652,560
- Issue date May 16, 2017
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processed texel cache
- Patent number 9,600,909
- Issue date Mar 21, 2017
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined transparent/non-transparent cache
- Patent number 9,529,544
- Issue date Dec 27, 2016
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translating cache hints
- Patent number 9,367,474
- Issue date Jun 14, 2016
- Apple Inc.
- Shailendra S. Desai
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System cache with sticky allocation
- Patent number 9,311,251
- Issue date Apr 12, 2016
- Apple Inc.
- Sukalpa Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined transparent/non-transparent cache
- Patent number 9,274,953
- Issue date Mar 1, 2016
- Apple Inc.
- James Wang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System cache with cache hint control
- Patent number 9,158,685
- Issue date Oct 13, 2015
- Apple Inc.
- Sukalpa Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer numerical storage format with precision type indicator
- Patent number 9,128,697
- Issue date Sep 8, 2015
- Apple Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System cache with quota-based control
- Patent number 9,043,570
- Issue date May 26, 2015
- Apple Inc.
- Sukalpa Biswas
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Combined transparent/non-transparent cache
- Patent number 8,977,818
- Issue date Mar 10, 2015
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System cache with sticky removal engine
- Patent number 8,886,886
- Issue date Nov 11, 2014
- Apple Inc.
- Sukalpa Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache implementing multiple replacement policies
- Patent number 8,719,509
- Issue date May 6, 2014
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic frequency control using coarse clock gating
- Patent number 8,671,380
- Issue date Mar 11, 2014
- Apple Inc.
- James Wang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Combined transparent/non-transparent cache
- Patent number 8,566,526
- Issue date Oct 22, 2013
- Apple Inc.
- James Wang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Credit management when resource granularity is larger than credit g...
- Patent number 8,400,924
- Issue date Mar 19, 2013
- Apple Inc.
- James Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
TLB prefetching
- Patent number 8,397,049
- Issue date Mar 12, 2013
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache implementing multiple replacement policies
- Patent number 8,392,658
- Issue date Mar 5, 2013
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer minimization in interface controller
- Patent number 8,284,792
- Issue date Oct 9, 2012
- Apple Inc.
- James Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Combined transparent/non-transparent cache
- Patent number 8,244,981
- Issue date Aug 14, 2012
- Apple Inc.
- James Wang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Block-based non-transparent cache
- Patent number 8,219,758
- Issue date Jul 10, 2012
- Apple Inc.
- James Wang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Digital phase relationship lock loop
- Patent number 8,078,772
- Issue date Dec 13, 2011
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Credit management when resource granularity is larger than credit g...
- Patent number 8,045,472
- Issue date Oct 25, 2011
- Apple Inc.
- James Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interface controller that has flexible configurability and low cost
- Patent number 7,930,462
- Issue date Apr 19, 2011
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital phase relationship lock loop
- Patent number 7,873,762
- Issue date Jan 18, 2011
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enqueue event first-in, first-out buffer (FIFO)
- Patent number 7,804,721
- Issue date Sep 28, 2010
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Combined Transparent/Non-Transparent Cache
- Publication number 20190171380
- Publication date Jun 6, 2019
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Graphical Processing Unit (GPU) Implementing a Plurality of Virtual...
- Publication number 20170329646
- Publication date Nov 16, 2017
- Apple Inc.
- Robert A. Drebin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Saving with Dynamic Pulse Insertion
- Publication number 20170244391
- Publication date Aug 24, 2017
- Apple Inc.
- James Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Combined Transparent/Non-Transparent Cache
- Publication number 20170132131
- Publication date May 11, 2017
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSED TEXEL CACHE
- Publication number 20170024905
- Publication date Jan 26, 2017
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combined Transparent/Non-Transparent Cache
- Publication number 20160170677
- Publication date Jun 16, 2016
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchical Phase Shift Apparatus for Array Antenna Weight Look Ah...
- Publication number 20160072186
- Publication date Mar 10, 2016
- James Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Combined Transparent/Non-Transparent Cache
- Publication number 20150149734
- Publication date May 28, 2015
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATING CACHE HINTS
- Publication number 20140372699
- Publication date Dec 18, 2014
- Shailendra S. Desai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM CACHE WITH STICKY REMOVAL ENGINE
- Publication number 20140095800
- Publication date Apr 3, 2014
- Apple Inc.
- Sukalpa Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM CACHE WITH CACHE HINT CONTROL
- Publication number 20140075125
- Publication date Mar 13, 2014
- Sukalpa Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM CACHE WITH QUOTA-BASED CONTROL
- Publication number 20140075118
- Publication date Mar 13, 2014
- Sukalpa Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM CACHE WITH STICKY ALLOCATION
- Publication number 20140059297
- Publication date Feb 27, 2014
- Sukalpa Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combined Transparent/Non-Transparent Cache
- Publication number 20140025900
- Publication date Jan 23, 2014
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Implementing Multiple Replacement Policies
- Publication number 20130151781
- Publication date Jun 13, 2013
- Apple Inc.
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtual GPU
- Publication number 20130021353
- Publication date Jan 24, 2013
- Apple Inc.
- Robert A. Drebin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Frequency Control Using Coarse Clock Gating
- Publication number 20130021072
- Publication date Jan 24, 2013
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combined Transparent/Non-Transparent Cache
- Publication number 20120278557
- Publication date Nov 1, 2012
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Credit Management When Resource Granularity is Larger than Credit G...
- Publication number 20120008500
- Publication date Jan 12, 2012
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital Phase Relationship Lock Loop
- Publication number 20110035518
- Publication date Feb 10, 2011
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combined Transparent/Non-Transparent Cache
- Publication number 20110010504
- Publication date Jan 13, 2011
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Implementing Multiple Replacement Policies
- Publication number 20110010502
- Publication date Jan 13, 2011
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block-Based Non-Transparent Cache
- Publication number 20110010520
- Publication date Jan 13, 2011
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TLB Prefetching
- Publication number 20110010521
- Publication date Jan 13, 2011
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Credit Management When Resource Granularity is Larger than Credit G...
- Publication number 20100165842
- Publication date Jul 1, 2010
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enqueue event first-In, first-out buffer (FIFO)
- Publication number 20090271545
- Publication date Oct 29, 2009
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital Phase Relationship Lock Loop
- Publication number 20090119531
- Publication date May 7, 2009
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interface Controller that has Flexible Configurability and Low Cost
- Publication number 20080300992
- Publication date Dec 4, 2008
- James Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffer Minimization in Interface Controller
- Publication number 20080298383
- Publication date Dec 4, 2008
- James Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Enqueue Event First-In, First-Out Buffer (FIFO)
- Publication number 20080198671
- Publication date Aug 21, 2008
- James Wang
- G06 - COMPUTING CALCULATING COUNTING

James H. P. Wang

Person

Patents Grantslast 30 patents

Combined transparent/non-transparent cache

Power saving with dynamic pulse insertion

Combined transparent/non-transparent cache

Graphical processing unit (GPU) implementing a plurality of virtual...

Graphical processing unit (GPU) implementing a plurality of virtual...

Non-blocking memory management unit

Processed texel cache

Combined transparent/non-transparent cache

Translating cache hints

System cache with sticky allocation

Combined transparent/non-transparent cache

System cache with cache hint control

Computer numerical storage format with precision type indicator

System cache with quota-based control

Combined transparent/non-transparent cache

System cache with sticky removal engine

Cache implementing multiple replacement policies

Dynamic frequency control using coarse clock gating

Combined transparent/non-transparent cache

Credit management when resource granularity is larger than credit g...

TLB prefetching

Cache implementing multiple replacement policies

Buffer minimization in interface controller

Combined transparent/non-transparent cache

Block-based non-transparent cache

Digital phase relationship lock loop

Credit management when resource granularity is larger than credit g...

Interface controller that has flexible configurability and low cost

Digital phase relationship lock loop

Enqueue event first-in, first-out buffer (FIFO)

Patents Applicationslast 30 patents

Combined Transparent/Non-Transparent Cache

Graphical Processing Unit (GPU) Implementing a Plurality of Virtual...

Power Saving with Dynamic Pulse Insertion

Combined Transparent/Non-Transparent Cache

PROCESSED TEXEL CACHE

Combined Transparent/Non-Transparent Cache

Hierarchical Phase Shift Apparatus for Array Antenna Weight Look Ah...

Combined Transparent/Non-Transparent Cache

TRANSLATING CACHE HINTS

SYSTEM CACHE WITH STICKY REMOVAL ENGINE

SYSTEM CACHE WITH CACHE HINT CONTROL

SYSTEM CACHE WITH QUOTA-BASED CONTROL

SYSTEM CACHE WITH STICKY ALLOCATION

Combined Transparent/Non-Transparent Cache

Cache Implementing Multiple Replacement Policies

Virtual GPU

Dynamic Frequency Control Using Coarse Clock Gating

Combined Transparent/Non-Transparent Cache

Credit Management When Resource Granularity is Larger than Credit G...

Digital Phase Relationship Lock Loop

Combined Transparent/Non-Transparent Cache

Cache Implementing Multiple Replacement Policies

Block-Based Non-Transparent Cache

TLB Prefetching

Credit Management When Resource Granularity is Larger than Credit G...

Enqueue event first-In, first-out buffer (FIFO)

Digital Phase Relationship Lock Loop

Interface Controller that has Flexible Configurability and Low Cost

Buffer Minimization in Interface Controller

Enqueue Event First-In, First-Out Buffer (FIFO)