James H. Scheuneman

Person

St. Paul, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Accessing control with predetermined priority based on a feedback a...
- Patent number 5,068,782
- Issue date Nov 26, 1991
- Unisys Corp.
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access system for pipelined data paths to and from storage
- Patent number 5,060,145
- Issue date Oct 22, 1991
- Unisys Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault capture/fault injection system
- Patent number 4,996,688
- Issue date Feb 26, 1991
- Unisys Corporation
- Larry L. Byers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined address check bit stack controller
- Patent number 4,989,210
- Issue date Jan 29, 1991
- Unisys Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus data transmission verification system
- Patent number 4,962,501
- Issue date Oct 9, 1990
- Unisys Corporation
- Larry L. Byers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unconditional clock and automatic refresh logic
- Patent number 4,953,131
- Issue date Aug 28, 1990
- Unisys Corporation
- David M. Purdham
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction check during write cycles
- Patent number 4,926,426
- Issue date May 15, 1990
- Unisys Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bank initiate error detection
- Patent number 4,918,696
- Issue date Apr 17, 1990
- Unisys Corporation
- David M. Purdham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Failure detection for partial write operations for memories
- Patent number 4,918,695
- Issue date Apr 17, 1990
- Unisys Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined data stack with access through-checking
- Patent number 4,757,440
- Issue date Jul 12, 1988
- Unisys Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for addressing a multibank memory system
- Patent number 4,727,510
- Issue date Feb 23, 1988
- Unisys Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple unit adapter
- Patent number 4,722,052
- Issue date Jan 26, 1988
- Sperry Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial duplication of pipelined stack with data integrity checking
- Patent number 4,697,233
- Issue date Sep 29, 1987
- Unisys Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple output port memory storage module
- Patent number 4,652,993
- Issue date Mar 24, 1987
- Sperry Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple port memory with port decode error detector
- Patent number 4,649,475
- Issue date Mar 10, 1987
- Sperry Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance storage unit
- Patent number 4,633,434
- Issue date Dec 30, 1986
- Sperry Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined split stack with high performance interleaved decode
- Patent number 4,600,986
- Issue date Jul 15, 1986
- Sperry Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory through checking system with comparison of data word parity...
- Patent number 4,531,213
- Issue date Jul 23, 1985
- Sperry Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hidden memory refresh
- Patent number 4,357,686
- Issue date Nov 2, 1982
- Sperry Corporation
- James H. Scheuneman
- G11 - INFORMATION STORAGE
Information Patent Grant
One word buffer memory system
- Patent number 4,292,674
- Issue date Sep 29, 1981
- Sperry Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double bit error correction using double bit complementing
- Patent number 4,163,147
- Issue date Jul 31, 1979
- Sperry Rand Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double bit error correction using single bit error correction, doub...
- Patent number 4,139,148
- Issue date Feb 13, 1979
- Sperry Rand Corporation
- James H. Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional bypass of error correction for dual memory access time...
- Patent number 4,112,502
- Issue date Sep 5, 1978
- Sperry Rand Corporation
- James Herman Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-write address word correction in cache memory system
- Patent number 4,092,713
- Issue date May 30, 1978
- Sperry Rand Corporation
- James Herman Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel requestor priority determination and requestor address mat...
- Patent number 4,070,706
- Issue date Jan 24, 1978
- Sperry Rand Corporation
- James Herman Scheuneman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional bypass of error correction for dual memory access time...
- Patent number 4,058,851
- Issue date Nov 15, 1977
- Sperry Rand Corporation
- James Herman Scheuneman
- G06 - COMPUTING CALCULATING COUNTING

James H. Scheuneman

Person

Patents Grantslast 30 patents

Accessing control with predetermined priority based on a feedback a...

Memory access system for pipelined data paths to and from storage

Fault capture/fault injection system

Pipelined address check bit stack controller

Bus data transmission verification system

Unconditional clock and automatic refresh logic

Error correction check during write cycles

Bank initiate error detection

Failure detection for partial write operations for memories

Pipelined data stack with access through-checking

System for addressing a multibank memory system

Multiple unit adapter

Partial duplication of pipelined stack with data integrity checking

Multiple output port memory storage module

Multiple port memory with port decode error detector

High performance storage unit

Pipelined split stack with high performance interleaved decode

Memory through checking system with comparison of data word parity...

Hidden memory refresh

One word buffer memory system

Double bit error correction using double bit complementing

Double bit error correction using single bit error correction, doub...

Conditional bypass of error correction for dual memory access time...

Post-write address word correction in cache memory system

Parallel requestor priority determination and requestor address mat...

Conditional bypass of error correction for dual memory access time...