James H. Stathis

Person

Poughquag, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Optimizating semiconductor binning by feed-forward process adjustment
- Patent number 11,869,783
- Issue date Jan 9, 2024
- International Business Machines Corporation
- Benjamin D. Briggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detection of performance degradation in integrated circuits
- Patent number 11,105,856
- Issue date Aug 31, 2021
- International Business Machines Corporation
- Emily A. Ray
- G01 - MEASURING TESTING
Information Patent Grant
Optimizing semiconductor binning by feed-forward process adjustment
- Patent number 11,049,744
- Issue date Jun 29, 2021
- International Business Machines Corporation
- Benjamin D. Briggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Magnetic tunnel junction performance monitoring based on magnetic f...
- Patent number 10,830,841
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Nicholas Anthony Lanzillo
- G01 - MEASURING TESTING
Information Patent Grant
Magnetic tunnel junction with low series resistance
- Patent number 10,796,833
- Issue date Oct 6, 2020
- International Business Machines Corporation
- Nicholas A. Lanzillo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Accelerated wafer testing using non-destructive and localized stress
- Patent number 10,746,782
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Benjamin D. Briggs
- G01 - MEASURING TESTING
Information Patent Grant
Accelerated wafer testing using non-destructive and localized stress
- Patent number 10,739,397
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Benjamin D. Briggs
- G01 - MEASURING TESTING
Information Patent Grant
Ring oscillator structures to determine local voltage value
- Patent number 10,574,240
- Issue date Feb 25, 2020
- International Business Machines Corporation
- Keith A. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-destructive analysis to determine use history of processor
- Patent number 10,552,278
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Keith A. Jenkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test structures for dielectric reliability evaluations
- Patent number 10,103,060
- Issue date Oct 16, 2018
- GLOBALFOUNDRIES Inc.
- David G. Brochu
- G01 - MEASURING TESTING
Information Patent Grant
Non-destructive analysis to determine use history of processor
- Patent number 10,102,090
- Issue date Oct 16, 2018
- International Business Machines Corporation
- Keith A. Jenkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining appropriateness of sampling integrated circuit test dat...
- Patent number 9,287,185
- Issue date Mar 15, 2016
- GLOBALFOUNDRIES Inc.
- Griselda Bonilla
- G01 - MEASURING TESTING
Information Patent Grant
Dielectric reliability assessment for advanced semiconductors
- Patent number 9,026,981
- Issue date May 5, 2015
- International Business Machines Corporation
- Baozhen Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dielectric reliability assessment for advanced semiconductors
- Patent number 8,839,180
- Issue date Sep 16, 2014
- International Business Machines Corporation
- Baozhen Li
- G01 - MEASURING TESTING
Information Patent Grant
Method for non-contact stress evaluation of wafer gate dielectric r...
- Patent number 6,602,772
- Issue date Aug 5, 2003
- International Business Machines Corporation
- Wagdi W. Abadeer
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for non-contact stress evaluation of wafer gat...
- Patent number 6,326,732
- Issue date Dec 4, 2001
- International Business Machines Corporation
- Wagdi W. Abadeer
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
OPTIMIZATING SEMICONDUCTOR BINNING BY FEED-FORWARD PROCESS ADJUSTMENT
- Publication number 20210249288
- Publication date Aug 12, 2021
- International Business Machines Corporation
- Benjamin D. Briggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTION OF PERFORMANCE DEGRADATION IN INTEGRATED CIRCUITS
- Publication number 20200150181
- Publication date May 14, 2020
- International Business Machines Corporation
- Emily A. Ray
- G01 - MEASURING TESTING
Information Patent Application
MAGNETIC TUNNEL JUNCTION WITH LOW SERIES RESISTANCE
- Publication number 20200098499
- Publication date Mar 26, 2020
- International Business Machines Corporation
- Nicholas A. Lanzillo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTIMIZATING SEMICONDUCTOR BINNING BY FEED-FORWARD PROCESS ADJUSTMENT
- Publication number 20190122911
- Publication date Apr 25, 2019
- International Business Machines Corporation
- Benjamin D. Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACCELERATED WAFER TESTING USING NON-DESTRUCTIVE AND LOCALIZED STRESS
- Publication number 20180328979
- Publication date Nov 15, 2018
- International Business Machines Corporation
- Benjamin D. Briggs
- G01 - MEASURING TESTING
Information Patent Application
ACCELERATED WAFER TESTING USING NON-DESTRUCTIVE AND LOCALIZED STRESS
- Publication number 20180328977
- Publication date Nov 15, 2018
- International Business Machines Corporation
- Benjamin D. Briggs
- G01 - MEASURING TESTING
Information Patent Application
NON-DESTRUCTIVE ANALYSIS TO DETERMINE USE HISTORY OF PROCESSOR
- Publication number 20180322025
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Keith A. Jenkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RING OSCILLATOR STRUCTURES TO DETERMINE LOCAL VOLTAGE VALUE
- Publication number 20180248555
- Publication date Aug 30, 2018
- International Business Machines Corporation
- Keith A. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NON-DESTRUCTIVE ANALYSIS TO DETERMINE USE HISTORY OF PROCESSOR
- Publication number 20170329685
- Publication date Nov 16, 2017
- International Business Machines Corporation
- Keith A. Jenkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST STRUCTURES FOR DIELECTRIC RELIABILITY EVALUATIONS
- Publication number 20160372389
- Publication date Dec 22, 2016
- GLOBALFOUNDRIES INC.
- David G. Brochu
- G01 - MEASURING TESTING
Information Patent Application
DIELECTRIC RELIABILITY ASSESSMENT FOR ADVANCED SEMICONDUCTORS
- Publication number 20140351785
- Publication date Nov 27, 2014
- BAOZHEN LI
- G01 - MEASURING TESTING
Information Patent Application
Method for non-contact stress evaluation of wafer gate dielectric r...
- Publication number 20020070675
- Publication date Jun 13, 2002
- Wagdi W. Abadeer
- G01 - MEASURING TESTING

James H. Stathis

Person

Patents Grantslast 30 patents

Optimizating semiconductor binning by feed-forward process adjustment

Detection of performance degradation in integrated circuits

Optimizing semiconductor binning by feed-forward process adjustment

Magnetic tunnel junction performance monitoring based on magnetic f...

Magnetic tunnel junction with low series resistance

Accelerated wafer testing using non-destructive and localized stress

Accelerated wafer testing using non-destructive and localized stress

Ring oscillator structures to determine local voltage value

Non-destructive analysis to determine use history of processor

Test structures for dielectric reliability evaluations

Non-destructive analysis to determine use history of processor

Determining appropriateness of sampling integrated circuit test dat...

Dielectric reliability assessment for advanced semiconductors

Dielectric reliability assessment for advanced semiconductors

Method for non-contact stress evaluation of wafer gate dielectric r...

Apparatus and method for non-contact stress evaluation of wafer gat...

Patents Applicationslast 30 patents

OPTIMIZATING SEMICONDUCTOR BINNING BY FEED-FORWARD PROCESS ADJUSTMENT

DETECTION OF PERFORMANCE DEGRADATION IN INTEGRATED CIRCUITS

MAGNETIC TUNNEL JUNCTION WITH LOW SERIES RESISTANCE

OPTIMIZATING SEMICONDUCTOR BINNING BY FEED-FORWARD PROCESS ADJUSTMENT

ACCELERATED WAFER TESTING USING NON-DESTRUCTIVE AND LOCALIZED STRESS

ACCELERATED WAFER TESTING USING NON-DESTRUCTIVE AND LOCALIZED STRESS

NON-DESTRUCTIVE ANALYSIS TO DETERMINE USE HISTORY OF PROCESSOR

RING OSCILLATOR STRUCTURES TO DETERMINE LOCAL VOLTAGE VALUE

NON-DESTRUCTIVE ANALYSIS TO DETERMINE USE HISTORY OF PROCESSOR

TEST STRUCTURES FOR DIELECTRIC RELIABILITY EVALUATIONS

DIELECTRIC RELIABILITY ASSESSMENT FOR ADVANCED SEMICONDUCTORS

Method for non-contact stress evaluation of wafer gate dielectric r...