James L. Ball

Person

Scotts Valley, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Network-on-chip (NOC) with flexible data width
- Patent number 11,700,002
- Issue date Jul 11, 2023
- Intel Corporation
- Sharath Raghava
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Three dimensional programmable logic circuit systems and methods
- Patent number 11,489,527
- Issue date Nov 1, 2022
- Intel Corporation
- Scott Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-purpose interface for configuration data and user fabric data
- Patent number 11,424,744
- Issue date Aug 23, 2022
- Intel Corporation
- Kevin Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Network-on-chip (NOC) with flexible data width
- Patent number 11,342,918
- Issue date May 24, 2022
- Intel Corporation
- Sharath Raghava
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interface for parallel configuration of programmable devices
- Patent number 11,223,361
- Issue date Jan 11, 2022
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Network-on-chip (NOC) with flexible data width
- Patent number 11,206,024
- Issue date Dec 21, 2021
- Intel Corporation
- Sharath Raghava
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-purpose interface for configuration data and user fabric data
- Patent number 10,833,679
- Issue date Nov 10, 2020
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Network-on-chip (NOC) with flexible data width
- Patent number 10,790,827
- Issue date Sep 29, 2020
- Intel Corporation
- Sharath Raghava
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interface for parallel configuration of programmable devices
- Patent number 10,666,265
- Issue date May 26, 2020
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for using scan storage circuits
- Patent number 9,588,176
- Issue date Mar 7, 2017
- Altera Corporation
- Michael Hutton
- G01 - MEASURING TESTING
Information Patent Grant
High-level language code sequence optimization for implementing pro...
- Patent number 9,329,847
- Issue date May 3, 2016
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplier operable to perform a variety of operations
- Patent number 9,223,743
- Issue date Dec 29, 2015
- Altera Corporation
- James L. Ball
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic device having a compressed configuration image stored on an i...
- Patent number 8,990,474
- Issue date Mar 24, 2015
- Altera Corporation
- James L. Ball
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Processors operable to allow flexible instruction alignment
- Patent number 8,874,881
- Issue date Oct 28, 2014
- Altera Corporation
- James Loran Ball
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level language code sequence optimization for implementing pro...
- Patent number 8,578,356
- Issue date Nov 5, 2013
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded memory data transformation circuitry
- Patent number 8,392,674
- Issue date Mar 5, 2013
- Altera Corporation
- James L. Ball
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for performing trace data compression
- Patent number 8,250,542
- Issue date Aug 21, 2012
- Altera Corporation
- James Loran Ball
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for reducing interrupt latency by using a dedic...
- Patent number 8,135,894
- Issue date Mar 13, 2012
- Altera Corporation
- James L. Ball
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors operable to allow flexible instruction alignment
- Patent number 8,006,071
- Issue date Aug 23, 2011
- Altera Corporation
- James Loran Ball
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level language code sequence optimization for implementing pro...
- Patent number 7,873,953
- Issue date Jan 18, 2011
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplier operable to perform a variety of operations
- Patent number 7,720,901
- Issue date May 18, 2010
- Altera Corporation
- James L. Ball
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular processor debug core connection for programmable chip systems
- Patent number 7,627,784
- Issue date Dec 1, 2009
- Altera Corporation
- Timothy P. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Invalidation of instruction cache line during reset handling
- Patent number 7,203,799
- Issue date Apr 10, 2007
- Altera Corporation
- James Loran Ball
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for controlling read and write streams in a circular FIFO bu...
- Patent number 6,567,094
- Issue date May 20, 2003
- Xerox Corporation
- Donald J. Curry
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Network-on-Chip (NOC) with Flexible Data Width
- Publication number 20230370068
- Publication date Nov 16, 2023
- Intel Corporation
- Sharath Raghava
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-PURPOSE INTERFACE FOR CONFIGURATION DATA AND USER FABRIC DATA
- Publication number 20230056118
- Publication date Feb 23, 2023
- Intel Corporation
- Kevin Clark
- G11 - INFORMATION STORAGE
Information Patent Application
NETWORK-ON-CHIP (NOC) WITH FLEXIBLE DATA WIDTH
- Publication number 20220116044
- Publication date Apr 14, 2022
- Intel Corporation
- Sharath Raghava
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Three Dimensional Programmable Logic Circuit Systems And Methods
- Publication number 20210313988
- Publication date Oct 7, 2021
- Intel Corporation
- Scott Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-PURPOSE INTERFACE FOR CONFIGURATION DATA AND USER FABRIC DATA
- Publication number 20210058085
- Publication date Feb 25, 2021
- Intel Corporation
- Kevin Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NETWORK-ON-CHIP (NOC) WITH FLEXIBLE DATA WIDTH
- Publication number 20210013887
- Publication date Jan 14, 2021
- Intel Corporation
- Sharath Raghava
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTERFACE FOR PARALLEL CONFIGURATION OF PROGRAMMABLE DEVICES
- Publication number 20200358444
- Publication date Nov 12, 2020
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-PURPOSE INTERFACE FOR CONFIGURATION DATA AND USER FABRIC DATA
- Publication number 20190140648
- Publication date May 9, 2019
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NETWORK-ON-CHIP (NOC) WITH FLEXIBLE DATA WIDTH
- Publication number 20190131975
- Publication date May 2, 2019
- Intel Corporation
- Sharath Raghava
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTERFACE FOR PARALLEL CONFIGURATION OF PROGRAMMABLE DEVICES
- Publication number 20190103872
- Publication date Apr 4, 2019
- Intel Corporation
- Kevin Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOGIC DEVICE HAVING A COMPRESSED CONFIGURATION IMAGE STORED ON AN I...
- Publication number 20130145074
- Publication date Jun 6, 2013
- Altera Corporation
- James L. Ball
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT
- Publication number 20110314265
- Publication date Dec 22, 2011
- Altera Corporation
- James Loran Ball
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimized processors and instruction alignment
- Publication number 20050223198
- Publication date Oct 6, 2005
- Altera Corporation
- James Loran Ball
- G06 - COMPUTING CALCULATING COUNTING

James L. Ball

Person

Patents Grantslast 30 patents

Network-on-chip (NOC) with flexible data width

Three dimensional programmable logic circuit systems and methods

Multi-purpose interface for configuration data and user fabric data

Network-on-chip (NOC) with flexible data width

Interface for parallel configuration of programmable devices

Network-on-chip (NOC) with flexible data width

Multi-purpose interface for configuration data and user fabric data

Network-on-chip (NOC) with flexible data width

Interface for parallel configuration of programmable devices

Techniques for using scan storage circuits

High-level language code sequence optimization for implementing pro...

Multiplier operable to perform a variety of operations

Logic device having a compressed configuration image stored on an i...

Processors operable to allow flexible instruction alignment

High-level language code sequence optimization for implementing pro...

Embedded memory data transformation circuitry

Method and apparatus for performing trace data compression

Methods and systems for reducing interrupt latency by using a dedic...

Processors operable to allow flexible instruction alignment

High-level language code sequence optimization for implementing pro...

Multiplier operable to perform a variety of operations

Modular processor debug core connection for programmable chip systems

Invalidation of instruction cache line during reset handling

System for controlling read and write streams in a circular FIFO bu...

Patents Applicationslast 30 patents

Network-on-Chip (NOC) with Flexible Data Width

MULTI-PURPOSE INTERFACE FOR CONFIGURATION DATA AND USER FABRIC DATA

NETWORK-ON-CHIP (NOC) WITH FLEXIBLE DATA WIDTH

Three Dimensional Programmable Logic Circuit Systems And Methods

MULTI-PURPOSE INTERFACE FOR CONFIGURATION DATA AND USER FABRIC DATA

NETWORK-ON-CHIP (NOC) WITH FLEXIBLE DATA WIDTH

INTERFACE FOR PARALLEL CONFIGURATION OF PROGRAMMABLE DEVICES

MULTI-PURPOSE INTERFACE FOR CONFIGURATION DATA AND USER FABRIC DATA

NETWORK-ON-CHIP (NOC) WITH FLEXIBLE DATA WIDTH

INTERFACE FOR PARALLEL CONFIGURATION OF PROGRAMMABLE DEVICES

LOGIC DEVICE HAVING A COMPRESSED CONFIGURATION IMAGE STORED ON AN I...

PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT

Optimized processors and instruction alignment