James M. Shehadi

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Interference testing
- Patent number 10,516,439
- Issue date Dec 24, 2019
- Intel Corporation
- Alexey Kostinsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preserving deterministic early valid across a clock domain crossing
- Patent number 10,025,732
- Issue date Jul 17, 2018
- Intel Corporation
- Stanley Steve Kulick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interference testing
- Patent number 9,722,663
- Issue date Aug 1, 2017
- Intel Corporation
- Alexey Kostinsky
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory subsystem command bus stress testing
- Patent number 9,009,540
- Issue date Apr 14, 2015
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory subsystem data bus stress testing
- Patent number 9,009,531
- Issue date Apr 14, 2015
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Functional memory array testing with a transaction-level test engine
- Patent number 9,003,246
- Issue date Apr 7, 2015
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Transaction-level testing of memory I/O and memory device
- Patent number 8,996,934
- Issue date Mar 31, 2015
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ADDRESS RANGE BASED IN-BAND MEMORY ERROR-CORRECTING CODE PROTECTION...
- Publication number 20190332469
- Publication date Oct 31, 2019
- Intel Corporation
- Amir A. RADJAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESERVING DETERMINISTIC EARLY VALID ACROSS A CLOCK DOMAIN CROSSING
- Publication number 20180095910
- Publication date Apr 5, 2018
- Intel Corporation
- Stanley Steve KULICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFERENCE TESTING
- Publication number 20170359099
- Publication date Dec 14, 2017
- Intel Corporation
- Alexey Kostinsky
- G01 - MEASURING TESTING
Information Patent Application
INTERFERENCE TESTING
- Publication number 20150280781
- Publication date Oct 1, 2015
- Intel Corporation
- Alexey Kostinsky
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MEMORY SUBSYSTEM DATA BUS STRESS TESTING
- Publication number 20140157053
- Publication date Jun 5, 2014
- CHRISTOPHER P. MOZAK
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SUBSYSTEM COMMAND BUS STRESS TESTING
- Publication number 20140157055
- Publication date Jun 5, 2014
- CHRISTOPHER P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL MEMORY ARRAY TESTING WITH A TRANSACTION-LEVEL TEST ENGINE
- Publication number 20140095947
- Publication date Apr 3, 2014
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSACTION-LEVEL TESTING OF MEMORY I/O AND MEMORY DEVICE
- Publication number 20140095946
- Publication date Apr 3, 2014
- Christopher P. Mozak
- G11 - INFORMATION STORAGE

James M. Shehadi

Person

Patents Grantslast 30 patents

Interference testing

Preserving deterministic early valid across a clock domain crossing

Interference testing

Memory subsystem command bus stress testing

Memory subsystem data bus stress testing

Functional memory array testing with a transaction-level test engine

Transaction-level testing of memory I/O and memory device

Patents Applicationslast 30 patents

ADDRESS RANGE BASED IN-BAND MEMORY ERROR-CORRECTING CODE PROTECTION...

PRESERVING DETERMINISTIC EARLY VALID ACROSS A CLOCK DOMAIN CROSSING

INTERFERENCE TESTING

INTERFERENCE TESTING

MEMORY SUBSYSTEM DATA BUS STRESS TESTING

MEMORY SUBSYSTEM COMMAND BUS STRESS TESTING

FUNCTIONAL MEMORY ARRAY TESTING WITH A TRANSACTION-LEVEL TEST ENGINE

TRANSACTION-LEVEL TESTING OF MEMORY I/O AND MEMORY DEVICE