James R. Vash

Person

Littleton, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processors having virtually clustered cores and cache slices
- Patent number 10,725,920
- Issue date Jul 28, 2020
- Intel Corporation
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors having virtually clustered cores and cache slices
- Patent number 10,725,919
- Issue date Jul 28, 2020
- Intel Corporation
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors having virtually clustered cores and cache slices
- Patent number 10,705,960
- Issue date Jul 7, 2020
- Intel Corporation
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors having virtually clustered cores and cache slices
- Patent number 10,073,779
- Issue date Sep 11, 2018
- Intel Corporation
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 10,019,366
- Issue date Jul 10, 2018
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 9,703,712
- Issue date Jul 11, 2017
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically controlling interconnect frequency in a processor
- Patent number 9,323,316
- Issue date Apr 26, 2016
- Intel Corporation
- Malini K. Bhandaru
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Inter-queue anti-starvation mechanism with dynamic deadlock avoidan...
- Patent number 9,304,922
- Issue date Apr 5, 2016
- Intel Corporation
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and methods for facilitating one-way ordering of...
- Patent number 9,288,260
- Issue date Mar 15, 2016
- Intel Corporation
- James R. Vash
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multiple-queue multiple-resource entry sleep and wakeup for power s...
- Patent number 9,207,753
- Issue date Dec 8, 2015
- Intel Corporation
- James R. Vash
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Directory cache supporting non-atomic input/output operations
- Patent number 9,170,946
- Issue date Oct 27, 2015
- Intel Corporation
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 9,058,271
- Issue date Jun 16, 2015
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Retry based protocol with source/receiver FIFO recovery and anti-st...
- Patent number 8,943,379
- Issue date Jan 27, 2015
- Intel Corporation
- James R. Vash
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Tunneling platform management messages through inter-processor inte...
- Patent number 8,904,079
- Issue date Dec 2, 2014
- Intel Corporation
- Luke Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-queue multiple-resource entry sleep and wakeup for power s...
- Patent number 8,868,951
- Issue date Oct 21, 2014
- Intel Corporation
- James R. Vash
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Monitoring thread synchronization in a distributed cache
- Patent number 8,769,211
- Issue date Jul 1, 2014
- Intel Corporation
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inter-queue anti-starvation mechanism with dynamic deadlock avoidan...
- Patent number 8,756,349
- Issue date Jun 17, 2014
- Intel Corporation
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 8,694,736
- Issue date Apr 8, 2014
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Inter-queue anti-starvation mechanism with dynamic deadlock avoidan...
- Patent number 8,626,968
- Issue date Jan 7, 2014
- Intel Corporation
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and methods for facilitating one-way ordering of...
- Patent number 8,554,851
- Issue date Oct 8, 2013
- Intel Corporation
- James R. Vash
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System-wide quiescence and per-thread transaction fence in a distri...
- Patent number 8,443,148
- Issue date May 14, 2013
- Intel Corporation
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core snoop handling during performance state and power state transi...
- Patent number 8,359,436
- Issue date Jan 22, 2013
- Intel Corporation
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting advanced RAS features in a secured computing system
- Patent number 8,301,907
- Issue date Oct 30, 2012
- Intel Corporation
- Mahesh S. Natu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 8,250,311
- Issue date Aug 21, 2012
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
- Publication number 20180225212
- Publication date Aug 9, 2018
- Intel Corporation
- Herbert H. HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
- Publication number 20180225213
- Publication date Aug 9, 2018
- Intel Corporation
- Herbert H. HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
- Publication number 20180225211
- Publication date Aug 9, 2018
- Intel Corporation
- Herbert H. HUM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20170308471
- Publication date Oct 26, 2017
- Intel Corporation
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20150178210
- Publication date Jun 25, 2015
- Intel Corporation
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER S...
- Publication number 20150160720
- Publication date Jun 11, 2015
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTER-QUEUE ANTI-STARVATION MECHANISM WITH DYNAMIC DEADLOCK AVOIDAN...
- Publication number 20140297967
- Publication date Oct 2, 2014
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, SYSTEM, AND METHODS FOR FACILITATINGONE-WAY ORDERING OF...
- Publication number 20140214955
- Publication date Jul 31, 2014
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY CONTROLLING INTERCONNECT FREQUENCY IN A PROCESSOR
- Publication number 20140208141
- Publication date Jul 24, 2014
- Malini K. Bhandaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
- Publication number 20140189239
- Publication date Jul 3, 2014
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS
- Publication number 20140181394
- Publication date Jun 26, 2014
- Herbert H. Hum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTER-QUEUE ANTI-STARVATION MECHANISM WITH DYNAMIC DEADLOCK AVOIDAN...
- Publication number 20140115197
- Publication date Apr 24, 2014
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20140115275
- Publication date Apr 24, 2014
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TUNNELING PLATFORM MANAGEMENT MESSAGES THROUGH INTER-PROCESSOR INTE...
- Publication number 20130346666
- Publication date Dec 26, 2013
- Luke Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20120317369
- Publication date Dec 13, 2012
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, SYSTEM, AND METHODS FOR FACILITATING ONE-WAY ORDERING OF...
- Publication number 20120079032
- Publication date Mar 29, 2012
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM-WIDE QUIESCENCE AND PER-THREAD TRANSACTION FENCE IN A DISTRI...
- Publication number 20110191542
- Publication date Aug 4, 2011
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING NON-OWNERSHIP LOAD REQUESTS HITTING MODIFIED LINE IN CAC...
- Publication number 20110161585
- Publication date Jun 30, 2011
- SAILESH KOTTAPALLI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER S...
- Publication number 20110161705
- Publication date Jun 30, 2011
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTER-QUEUE ANTI-STARVATION MECHANISM WITH DYNAMIC DEADLOCK AVOIDAN...
- Publication number 20110161601
- Publication date Jun 30, 2011
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETRY BASED PROTOCOL WITH SOURCE/RECEIVER FIFO RECOVERY AND ANTI-ST...
- Publication number 20110161769
- Publication date Jun 30, 2011
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CORE SNOOP HANDLING DURING PERFORMANCE STATE AND POWER STATE TRANSI...
- Publication number 20110153924
- Publication date Jun 23, 2011
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR MONITORING SYNCHRONIZATION IN A...
- Publication number 20110153948
- Publication date Jun 23, 2011
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20100005246
- Publication date Jan 7, 2010
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING ADVANCED RAS FEATURES IN A SECURED COMPUTING SYSTEM
- Publication number 20090089566
- Publication date Apr 2, 2009
- Mahesh S. Natu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Advanced load address table buffer
- Publication number 20060242390
- Publication date Oct 26, 2006
- Intel Corporation
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING

James R. Vash

Person

Patents Grantslast 30 patents

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Satisfying memory ordering requirements between partial reads and n...

Satisfying memory ordering requirements between partial reads and n...

Dynamically controlling interconnect frequency in a processor

Inter-queue anti-starvation mechanism with dynamic deadlock avoidan...

Apparatus, system, and methods for facilitating one-way ordering of...

Multiple-queue multiple-resource entry sleep and wakeup for power s...

Directory cache supporting non-atomic input/output operations

Satisfying memory ordering requirements between partial reads and n...

Retry based protocol with source/receiver FIFO recovery and anti-st...

Tunneling platform management messages through inter-processor inte...

Multiple-queue multiple-resource entry sleep and wakeup for power s...

Monitoring thread synchronization in a distributed cache

Inter-queue anti-starvation mechanism with dynamic deadlock avoidan...

Satisfying memory ordering requirements between partial reads and n...

Inter-queue anti-starvation mechanism with dynamic deadlock avoidan...

Apparatus, system, and methods for facilitating one-way ordering of...

System-wide quiescence and per-thread transaction fence in a distri...

Core snoop handling during performance state and power state transi...

Supporting advanced RAS features in a secured computing system

Satisfying memory ordering requirements between partial reads and n...

Patents Applicationslast 30 patents

PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES

PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES

PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER S...

INTER-QUEUE ANTI-STARVATION MECHANISM WITH DYNAMIC DEADLOCK AVOIDAN...

APPARATUS, SYSTEM, AND METHODS FOR FACILITATINGONE-WAY ORDERING OF...

DYNAMICALLY CONTROLLING INTERCONNECT FREQUENCY IN A PROCESSOR

PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES

DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS

INTER-QUEUE ANTI-STARVATION MECHANISM WITH DYNAMIC DEADLOCK AVOIDAN...

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

TUNNELING PLATFORM MANAGEMENT MESSAGES THROUGH INTER-PROCESSOR INTE...

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

APPARATUS, SYSTEM, AND METHODS FOR FACILITATING ONE-WAY ORDERING OF...

SYSTEM-WIDE QUIESCENCE AND PER-THREAD TRANSACTION FENCE IN A DISTRI...

PROCESSING NON-OWNERSHIP LOAD REQUESTS HITTING MODIFIED LINE IN CAC...

MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER S...

INTER-QUEUE ANTI-STARVATION MECHANISM WITH DYNAMIC DEADLOCK AVOIDAN...

RETRY BASED PROTOCOL WITH SOURCE/RECEIVER FIFO RECOVERY AND ANTI-ST...

CORE SNOOP HANDLING DURING PERFORMANCE STATE AND POWER STATE TRANSI...

SYSTEMS, METHODS, AND APPARATUS FOR MONITORING SYNCHRONIZATION IN A...

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

SUPPORTING ADVANCED RAS FEATURES IN A SECURED COMPUTING SYSTEM

Advanced load address table buffer