James S. Blomgren

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Shared register architecture for a dual-instruction-set CPU to faci...
- Patent number 6,076,155
- Issue date Jun 13, 2000
- S3 Incorporated
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RAM-like test structure superimposed over rows of macrocells with a...
- Patent number 5,951,702
- Issue date Sep 14, 1999
- S3 Incorporated
- Hank Lim
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiplier with selectable booth encoders for performing 3D graphic...
- Patent number 5,935,198
- Issue date Aug 10, 1999
- S3 Incorporated
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temporal re-alignment of a floating point pipeline to an integer pi...
- Patent number 5,884,057
- Issue date Mar 16, 1999
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug and video queue for multi-processor chip
- Patent number 5,848,264
- Issue date Dec 8, 1998
- S3 Incorporated
- Brian R. Baird
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with a large cache shared by redundant CPUs for incr...
- Patent number 5,828,578
- Issue date Oct 27, 1998
- S3 Incorporated
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extenstion of 32-bit architecture for 64-bit addressing with shared...
- Patent number 5,826,074
- Issue date Oct 20, 1998
- S3 Incorporated
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early instruction-length pre-decode of variable-length instructions...
- Patent number 5,809,272
- Issue date Sep 15, 1998
- Exponential Technology Inc.
- Shalesh Thusoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-instruction-set CPU having shared register for storing data be...
- Patent number 5,805,918
- Issue date Sep 8, 1998
- S3 Incorporated
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed-modulo address generation using shadow segment registers
- Patent number 5,790,443
- Issue date Aug 4, 1998
- S3 Incorporated
- Gene Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced register-dependency checking for paired-instruction dispatc...
- Patent number 5,790,826
- Issue date Aug 4, 1998
- S3 Incorporated
- Shalesh Thusoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Merge/mask, rotate/shift, and boolean operations from two instructi...
- Patent number 5,781,457
- Issue date Jul 14, 1998
- Exponential Technology, Inc.
- Earl T. Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-instruction-set architecture CPU with hidden software emulatio...
- Patent number 5,781,750
- Issue date Jul 14, 1998
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor DRAM controller that prioritizes row-miss requests...
- Patent number 5,745,913
- Issue date Apr 28, 1998
- Exponential Technology, Inc.
- Jay C. Pattin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-testing multi-processor die with internal compare points
- Patent number 5,732,209
- Issue date Mar 24, 1998
- Exponential Technology, Inc.
- Peter J. Vigil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stack push/pop tracking and pairing in a pipelined processor
- Patent number 5,687,336
- Issue date Nov 11, 1997
- Exponential Technology, Inc.
- Gene Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared floating-point registers and register port-pairing in a dual...
- Patent number 5,685,009
- Issue date Nov 4, 1997
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for emulating multiple debug breakpoints by page partitionin...
- Patent number 5,664,159
- Issue date Sep 2, 1997
- Exponential Technology, Inc.
- David E. Richter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translator having segment bounds encoding for storage in a TLB
- Patent number 5,652,872
- Issue date Jul 29, 1997
- Exponential Technology, Inc.
- David E. Richter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inexact leading-one/leading-zero prediction integrated with a float...
- Patent number 5,633,819
- Issue date May 27, 1997
- Exponential Technology, Inc.
- Cheryl S. Brashears
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Splitting a floating-point stack-exchange instruction for merging i...
- Patent number 5,634,118
- Issue date May 27, 1997
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block-based branch prediction using a target finder array storing t...
- Patent number 5,608,886
- Issue date Mar 4, 1997
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-architecture super-scalar pipeline
- Patent number 5,598,546
- Issue date Jan 28, 1997
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Program watchpoint checking using paging with sub-page validity
- Patent number 5,598,553
- Issue date Jan 28, 1997
- Exponential Technology, Inc.
- David E. Richter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Master-slave cache system for instruction and data cache memories
- Patent number 5,551,001
- Issue date Aug 27, 1996
- Exponential Technology, Inc.
- Earl T. Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floating point exception prediction for compound operations and var...
- Patent number 5,548,545
- Issue date Aug 20, 1996
- Exponential Technology, Inc.
- Cheryl S. Brashears
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual instruction set processor having a pipeline with a pipestage f...
- Patent number 5,542,059
- Issue date Jul 30, 1996
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address tracking and branch resolution in a processor with multiple...
- Patent number 5,542,109
- Issue date Jul 30, 1996
- Exponential Technology, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced-modulus address generation using sign-extension and correction
- Patent number 5,511,017
- Issue date Apr 23, 1996
- Exponential Technology, Inc.
- Earl T. Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Emulating operating system calls in an alternate instruction set us...
- Patent number 5,481,684
- Issue date Jan 2, 1996
- Exponential Technology, Inc.
- David E. Richter
- G06 - COMPUTING CALCULATING COUNTING

James S. Blomgren

Person

Patents Grantslast 30 patents

Shared register architecture for a dual-instruction-set CPU to faci...

RAM-like test structure superimposed over rows of macrocells with a...

Multiplier with selectable booth encoders for performing 3D graphic...

Temporal re-alignment of a floating point pipeline to an integer pi...

Debug and video queue for multi-processor chip

Microprocessor with a large cache shared by redundant CPUs for incr...

Extenstion of 32-bit architecture for 64-bit addressing with shared...

Early instruction-length pre-decode of variable-length instructions...

Dual-instruction-set CPU having shared register for storing data be...

Mixed-modulo address generation using shadow segment registers

Reduced register-dependency checking for paired-instruction dispatc...

Merge/mask, rotate/shift, and boolean operations from two instructi...

Dual-instruction-set architecture CPU with hidden software emulatio...

Multi-processor DRAM controller that prioritizes row-miss requests...

Self-testing multi-processor die with internal compare points

Stack push/pop tracking and pairing in a pipelined processor

Shared floating-point registers and register port-pairing in a dual...

Method for emulating multiple debug breakpoints by page partitionin...

Translator having segment bounds encoding for storage in a TLB

Inexact leading-one/leading-zero prediction integrated with a float...

Splitting a floating-point stack-exchange instruction for merging i...

Block-based branch prediction using a target finder array storing t...

Dual-architecture super-scalar pipeline

Program watchpoint checking using paging with sub-page validity

Master-slave cache system for instruction and data cache memories

Floating point exception prediction for compound operations and var...

Dual instruction set processor having a pipeline with a pipestage f...

Address tracking and branch resolution in a processor with multiple...

Reduced-modulus address generation using sign-extension and correction

Emulating operating system calls in an alternate instruction set us...