James Vernon Rhodes

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Electromechanical module, for holding IC-chips in a chip testing sy...
- Patent number 6,958,617
- Issue date Oct 25, 2005
- Unisys Corporation
- James Vernon Rhodes
- G01 - MEASURING TESTING
Information Patent Grant
System for testing one or more groups of IC-chips while concurrentl...
- Patent number 6,924,636
- Issue date Aug 2, 2005
- Unisys Corporation
- Randy Neaman Siade
- G01 - MEASURING TESTING
Information Patent Grant
System for testing a group of IC-chips having a chip holding subass...
- Patent number 6,919,718
- Issue date Jul 19, 2005
- Unisys Corporation
- Randy Neaman Siade
- G01 - MEASURING TESTING
Information Patent Grant
System for testing multiple groups of IC-chips which concurrently s...
- Patent number 6,909,299
- Issue date Jun 21, 2005
- Unisys Corporation
- Randy Neaman Siade
- G01 - MEASURING TESTING
Information Patent Grant
Initial stage of a multi-stage algorithmic pattern generator for te...
- Patent number 6,571,365
- Issue date May 27, 2003
- Unisys Corporation
- James Vernon Rhodes
- G01 - MEASURING TESTING
Information Patent Grant
Output stage of a multi-stage algorithmic pattern generator for tes...
- Patent number 6,480,981
- Issue date Nov 12, 2002
- Unisys Corporation
- James Vernon Rhodes
- G01 - MEASURING TESTING
Information Patent Grant
Intermediate stage of a multi-stage algorithmic pattern generator f...
- Patent number 6,477,676
- Issue date Nov 5, 2002
- Unisys Corporation
- James Vernon Rhodes
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-stage algorithmic pattern generator for testing IC chips
- Patent number 6,415,408
- Issue date Jul 2, 2002
- Unisys Corporation
- James Vernon Rhodes
- G01 - MEASURING TESTING
Information Patent Grant
System for testing IC chips selectively with stored or internally g...
- Patent number 6,415,409
- Issue date Jul 2, 2002
- Unisys Corporation
- James Vernon Rhodes
- G01 - MEASURING TESTING
Information Patent Grant
Program storage device containing instructions that are spaced apar...
- Patent number 6,405,150
- Issue date Jun 11, 2002
- Unisys Corporation
- James Vernon Rhodes
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic system for testing a set of multiple chips concurrently...
- Patent number 6,363,504
- Issue date Mar 26, 2002
- Unisys Corporation
- James Vernon Rhodes
- G01 - MEASURING TESTING
Information Patent Grant
Electronic system for testing chips having a selectable number of p...
- Patent number 6,363,510
- Issue date Mar 26, 2002
- Unisys Corporation
- James Vernon Rhodes
- G01 - MEASURING TESTING
Information Patent Grant
Universal burn-in driver system and method therefor
- Patent number 5,557,559
- Issue date Sep 17, 1996
- Motay Electronics, Inc.
- James V. Rhodes
- G01 - MEASURING TESTING
Information Patent Grant
Universal burn-in driver system and method therefor
- Patent number 5,390,129
- Issue date Feb 14, 1995
- Motay Electronics, Inc.
- James V. Rhodes
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM FOR TESTING ONE OR MORE GROUPS OF IC-CHIPS WHILE CONCURRENTL...
- Publication number 20050099174
- Publication date May 12, 2005
- UNISYS CORPORATION
- Randy Neaman Siade
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR TESTING A GROUP OF IC-CHIPS HAVING A CHIP HOLDING SUBASS...
- Publication number 20050099173
- Publication date May 12, 2005
- UNISYS CORPORATION
- Randy Neaman Siade
- G01 - MEASURING TESTING

James Vernon Rhodes

Person

Patents Grantslast 30 patents

Electromechanical module, for holding IC-chips in a chip testing sy...

System for testing one or more groups of IC-chips while concurrentl...

System for testing a group of IC-chips having a chip holding subass...

System for testing multiple groups of IC-chips which concurrently s...

Initial stage of a multi-stage algorithmic pattern generator for te...

Output stage of a multi-stage algorithmic pattern generator for tes...

Intermediate stage of a multi-stage algorithmic pattern generator f...

Multi-stage algorithmic pattern generator for testing IC chips

System for testing IC chips selectively with stored or internally g...

Program storage device containing instructions that are spaced apar...

Electronic system for testing a set of multiple chips concurrently...

Electronic system for testing chips having a selectable number of p...

Universal burn-in driver system and method therefor

Universal burn-in driver system and method therefor

Patents Applicationslast 30 patents

SYSTEM FOR TESTING ONE OR MORE GROUPS OF IC-CHIPS WHILE CONCURRENTL...

SYSTEM FOR TESTING A GROUP OF IC-CHIPS HAVING A CHIP HOLDING SUBASS...