James W. Alexander

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power management circuit with per activity weighting and multiple t...
- Patent number 10,073,659
- Issue date Sep 11, 2018
- Intel Corporation
- James Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic link width modulation
- Patent number 10,037,069
- Issue date Jul 31, 2018
- Intel Corporation
- Neven M. Abou Gazala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Profiling a job power and energy consumption for a data processing...
- Patent number 9,927,857
- Issue date Mar 27, 2018
- Intel Corporation
- Justin J. Song
- G05 - CONTROLLING REGULATING
Information Patent Grant
Power aware job scheduler and manager for a data processing system
- Patent number 9,921,633
- Issue date Mar 20, 2018
- Intel Corporation
- Devadatta V. (Deva) Bodas
- G05 - CONTROLLING REGULATING
Information Patent Grant
Adjustment of execution of tasks
- Patent number 9,588,823
- Issue date Mar 7, 2017
- Intel Corporation
- Muralidhar Rajappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to estimate power performance of a job that r...
- Patent number 9,575,536
- Issue date Feb 21, 2017
- Intel Corporation
- Muralidhar Rajappa
- G05 - CONTROLLING REGULATING
Information Patent Grant
Controlling power consumption in processor-based systems and compon...
- Patent number 9,568,978
- Issue date Feb 14, 2017
- Intel Corporation
- James S. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic link width adjustment
- Patent number 9,292,465
- Issue date Mar 22, 2016
- Intel Corporation
- Malay Trivedi
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Dynamic link width modulation
- Patent number 9,280,194
- Issue date Mar 8, 2016
- Intel Corporation
- Neven M. Abou Gazala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Adaptive low-power link-state entry policy for active interconnect...
- Patent number 9,256,268
- Issue date Feb 9, 2016
- Intel Corporation
- Ren Wang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Exposing protected memory addresses
- Patent number 9,195,404
- Issue date Nov 24, 2015
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing power and latency on a link
- Patent number 8,935,578
- Issue date Jan 13, 2015
- Intel Corporation
- James W. Alexander
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Optimizing performance and power consumption during memory power do...
- Patent number 8,719,606
- Issue date May 6, 2014
- Intel Corporation
- Son H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system to improve the operations of a registered memory...
- Patent number 8,661,284
- Issue date Feb 25, 2014
- Intel Corporation
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory power management via dynamic memory operation states
- Patent number 8,438,410
- Issue date May 7, 2013
- Intel Corporation
- Howard S. David
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Systems, methods and apparatuses for clock enable (CKE) coordination
- Patent number 8,429,367
- Issue date Apr 23, 2013
- Intel Corporation
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system to improve the operations of a registered memory...
- Patent number 8,375,241
- Issue date Feb 12, 2013
- Intel Corporation
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Mechanism for adjacent-symbol error correction and detection
- Patent number 8,327,222
- Issue date Dec 4, 2012
- Intel Corporation
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Fully buffered DIMM read data substitution for write acknowledgement
- Patent number 7,941,618
- Issue date May 10, 2011
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods and apparatuses for rank coordination
- Patent number 7,885,914
- Issue date Feb 8, 2011
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resource power controller to return a resource to an up state based...
- Patent number 7,865,753
- Issue date Jan 4, 2011
- Intel Corporation
- James W. Alexander
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method for memory phase shedding
- Patent number 7,804,733
- Issue date Sep 28, 2010
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mitigating silent data corruption in a buffered memory module archi...
- Patent number 7,734,980
- Issue date Jun 8, 2010
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Silent data corruption mitigation using error correction code with...
- Patent number 7,644,347
- Issue date Jan 5, 2010
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory replay mechanism
- Patent number 7,587,625
- Issue date Sep 8, 2009
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronized memory channels with unidirectional links
- Patent number 7,516,349
- Issue date Apr 7, 2009
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for adjacent-symbol error correction and detection
- Patent number 7,509,560
- Issue date Mar 24, 2009
- Intel Corporation
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Fully buffered DIMM read data substitution for write acknowledgement
- Patent number 7,444,479
- Issue date Oct 28, 2008
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory channel utilizing permuting status patterns
- Patent number 7,200,787
- Issue date Apr 3, 2007
- Intel Corporation
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing a logic device
- Patent number 6,615,379
- Issue date Sep 2, 2003
- Intel Corporation
- Michael J. Tripp
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC LINK WIDTH MODULATION
- Publication number 20170003730
- Publication date Jan 5, 2017
- Intel Corporation
- Neven M. Abou Gazala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT CIRCUIT WITH PER ACTIVITY WEIGHTING AND MULTIPLE T...
- Publication number 20160378172
- Publication date Dec 29, 2016
- James Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTMENT OF EXECUTION OF TASKS
- Publication number 20160188379
- Publication date Jun 30, 2016
- Intel Corporation
- Muralidhar Rajappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus to Manage Jobs that can and Cannot be Suspend...
- Publication number 20160054781
- Publication date Feb 25, 2016
- Intel Corporation
- Muralidhar Rajappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER AWARE JOB SCHEDULER AND MANAGER FOR A DATA PROCESSING SYSTEM
- Publication number 20160054780
- Publication date Feb 25, 2016
- Intel Corporation
- Devadatta V. (Deva) Bodas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROFILING A JOB POWER AND ENERGY CONSUMPTION FOR A DATA PROCESSING...
- Publication number 20160054774
- Publication date Feb 25, 2016
- Intel Corporation
- Justin J. Song
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO ESTIMATE POWER PERFORMANCE OF A JOB THAT R...
- Publication number 20160054775
- Publication date Feb 25, 2016
- Muralidhar Rajappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO GENERATE AND USE POWER, THERMAL AND PERFORM...
- Publication number 20160054783
- Publication date Feb 25, 2016
- Intel Corporation
- Muralidhar Rajappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXPOSING PROTECTED MEMORY ADDRESSES
- Publication number 20150169224
- Publication date Jun 18, 2015
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Power Consumption in Processor-Based Systems and Compon...
- Publication number 20150089254
- Publication date Mar 26, 2015
- James S. Burns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE LOW-POWER LINK-STATE ENTRY POLICY FOR ACTIVE INTERCONNECT...
- Publication number 20140195833
- Publication date Jul 10, 2014
- Ren Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR OPTIMIZING POWER AND LATENCY ON A LINK
- Publication number 20140095944
- Publication date Apr 3, 2014
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC LINK WIDTH ADJUSTMENT
- Publication number 20140019654
- Publication date Jan 16, 2014
- Malay Trivedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC LINK WIDTH MODULATION
- Publication number 20130346772
- Publication date Dec 26, 2013
- Neven M. Abou Gazala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY...
- Publication number 20130145197
- Publication date Jun 6, 2013
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY POWER MANAGEMENT VIA DYNAMIC MEMORY OPERATION STATES
- Publication number 20110320839
- Publication date Dec 29, 2011
- Howard S. David
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY...
- Publication number 20100257398
- Publication date Oct 7, 2010
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING AN INTEGRATED MEMORY CONTROLLER TO TRANSPARENTLY WORK WITH...
- Publication number 20100169729
- Publication date Jul 1, 2010
- SHAMANNA M. DATTA
- G11 - INFORMATION STORAGE
Information Patent Application
OPTIMIZING PERFORMANCE AND POWER CONSUMPTION DURING MEMORY POWER DO...
- Publication number 20090249097
- Publication date Oct 1, 2009
- Son H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS, METHODS AND APPARATUSES FOR RANK COORDINATION
- Publication number 20090171875
- Publication date Jul 2, 2009
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MEMORY PHASE SHEDDING
- Publication number 20090172442
- Publication date Jul 2, 2009
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COUPLED LOW POWER STATE ENTRY AND EXIT FOR LINKS AND MEMORY
- Publication number 20090172440
- Publication date Jul 2, 2009
- Krishna Kant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS AND APPARATUSES FOR CLOCK ENABLE (CKE) COORDINATION
- Publication number 20090172681
- Publication date Jul 2, 2009
- Intel Corporation
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Application
HARDWARE PROACTIVE IMPLEMENTATION FOR ACTIVE MODE POWER CONTROL OF...
- Publication number 20090172441
- Publication date Jul 2, 2009
- Krishna Kant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for Adjacent-Symbol Error Correction and Detection
- Publication number 20090125786
- Publication date May 14, 2009
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Application
FULLY BUFFERED DIMM READ DATA SUBSTITUTION FOR WRITE ACKNOWLEDGEMENT
- Publication number 20080320249
- Publication date Dec 25, 2008
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resource power controller
- Publication number 20080244291
- Publication date Oct 2, 2008
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chipset determinism for improved validation
- Publication number 20080005378
- Publication date Jan 3, 2008
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory replay mechanism
- Publication number 20070226579
- Publication date Sep 27, 2007
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Synchronized memory channels with unidirectional links
- Publication number 20070156993
- Publication date Jul 5, 2007
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING

James W. Alexander

Person

Patents Grantslast 30 patents

Power management circuit with per activity weighting and multiple t...

Dynamic link width modulation

Profiling a job power and energy consumption for a data processing...

Power aware job scheduler and manager for a data processing system

Adjustment of execution of tasks

Methods and apparatus to estimate power performance of a job that r...

Controlling power consumption in processor-based systems and compon...

Dynamic link width adjustment

Dynamic link width modulation

Adaptive low-power link-state entry policy for active interconnect...

Exposing protected memory addresses

Method and apparatus for optimizing power and latency on a link

Optimizing performance and power consumption during memory power do...

Method and system to improve the operations of a registered memory...

Memory power management via dynamic memory operation states

Systems, methods and apparatuses for clock enable (CKE) coordination

Method and system to improve the operations of a registered memory...

Mechanism for adjacent-symbol error correction and detection

Fully buffered DIMM read data substitution for write acknowledgement

Systems, methods and apparatuses for rank coordination

Resource power controller to return a resource to an up state based...

System and method for memory phase shedding

Mitigating silent data corruption in a buffered memory module archi...

Silent data corruption mitigation using error correction code with...

Memory replay mechanism

Synchronized memory channels with unidirectional links

Mechanism for adjacent-symbol error correction and detection

Fully buffered DIMM read data substitution for write acknowledgement

Memory channel utilizing permuting status patterns

Method and apparatus for testing a logic device

Patents Applicationslast 30 patents

DYNAMIC LINK WIDTH MODULATION

POWER MANAGEMENT CIRCUIT WITH PER ACTIVITY WEIGHTING AND MULTIPLE T...

ADJUSTMENT OF EXECUTION OF TASKS

Methods and Apparatus to Manage Jobs that can and Cannot be Suspend...

POWER AWARE JOB SCHEDULER AND MANAGER FOR A DATA PROCESSING SYSTEM

PROFILING A JOB POWER AND ENERGY CONSUMPTION FOR A DATA PROCESSING...

METHODS AND APPARATUS TO ESTIMATE POWER PERFORMANCE OF A JOB THAT R...

METHOD AND APPARATUS TO GENERATE AND USE POWER, THERMAL AND PERFORM...

EXPOSING PROTECTED MEMORY ADDRESSES

Controlling Power Consumption in Processor-Based Systems and Compon...

ADAPTIVE LOW-POWER LINK-STATE ENTRY POLICY FOR ACTIVE INTERCONNECT...

METHOD AND APPARATUS FOR OPTIMIZING POWER AND LATENCY ON A LINK

DYNAMIC LINK WIDTH ADJUSTMENT

DYNAMIC LINK WIDTH MODULATION

METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY...

MEMORY POWER MANAGEMENT VIA DYNAMIC MEMORY OPERATION STATES

METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY...

ENABLING AN INTEGRATED MEMORY CONTROLLER TO TRANSPARENTLY WORK WITH...

OPTIMIZING PERFORMANCE AND POWER CONSUMPTION DURING MEMORY POWER DO...

SYSTEMS, METHODS AND APPARATUSES FOR RANK COORDINATION

SYSTEM AND METHOD FOR MEMORY PHASE SHEDDING

COUPLED LOW POWER STATE ENTRY AND EXIT FOR LINKS AND MEMORY

SYSTEMS, METHODS AND APPARATUSES FOR CLOCK ENABLE (CKE) COORDINATION

HARDWARE PROACTIVE IMPLEMENTATION FOR ACTIVE MODE POWER CONTROL OF...

Mechanism for Adjacent-Symbol Error Correction and Detection

FULLY BUFFERED DIMM READ DATA SUBSTITUTION FOR WRITE ACKNOWLEDGEMENT

Resource power controller

Chipset determinism for improved validation

Memory replay mechanism

Synchronized memory channels with unidirectional links