James W. Bishop

Person

Endwell, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Constrained carries on speculative counters
- Patent number 11,620,134
- Issue date Apr 4, 2023
- International Business Machines Corporation
- Dan Buerkle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operation of a multi-slice processor implementing a hardware level...
- Patent number 11,138,050
- Issue date Oct 5, 2021
- International Business Machines Corporation
- Brian D. Barrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Saving and restoring a transaction memory state
- Patent number 10,996,995
- Issue date May 4, 2021
- International Business Machines Corporation
- Steven J. Battle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread migration using a microcode engine of a multi-slice processor
- Patent number 10,387,154
- Issue date Aug 20, 2019
- International Business Machines Corporation
- James W. Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operation of a multi-slice processor implementing a hardware level...
- Patent number 10,318,356
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Brian D. Barrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ECC scrubbing method in a multi-slice microprocessor
- Patent number 10,223,196
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Brian D. Barrick
- G11 - INFORMATION STORAGE
Information Patent Grant
In-pipe error scrubbing within a processor core
- Patent number 9,928,128
- Issue date Mar 27, 2018
- International Business Machines Corporation
- Brian D. Barrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ECC scrubbing in a multi-slice microprocessor
- Patent number 9,846,614
- Issue date Dec 19, 2017
- International Business Machines Corporation
- Brian D. Barrick
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensor array packaging solution
- Patent number 9,389,103
- Issue date Jul 12, 2016
- Lockheed Martin Corporation
- James E. Bishop
- G01 - MEASURING TESTING
Information Patent Grant
Region-weighted accounting of multi-threaded processor core accordi...
- Patent number 9,110,708
- Issue date Aug 18, 2015
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Region-weighted accounting of multi-threaded processor core accordi...
- Patent number 9,015,449
- Issue date Apr 21, 2015
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor including age tracking of issue queue instructions
- Patent number 8,489,863
- Issue date Jul 16, 2013
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread priority method for ensuring processing fairness in simultan...
- Patent number 8,418,180
- Issue date Apr 9, 2013
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor including age tracking of issue queue instructions
- Patent number 8,380,964
- Issue date Feb 19, 2013
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selecting fixed-point instructions to issue on load-store unit
- Patent number 8,108,655
- Issue date Jan 31, 2012
- International Business Machines Corporation
- Christopher Michael Abernathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information handling system including a processor with a bifurcated...
- Patent number 8,103,852
- Issue date Jan 24, 2012
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for implementing a hardware-supported thread assi...
- Patent number 7,779,234
- Issue date Aug 17, 2010
- International Business Machines Corporation
- James W. Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread priority method for ensuring processing fairness in simultan...
- Patent number 7,631,308
- Issue date Dec 8, 2009
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods to randomly or pseudo-randomly, without bias, select instru...
- Patent number 7,620,801
- Issue date Nov 17, 2009
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for checkpointing instruction groups with out-of-order float...
- Patent number 7,478,276
- Issue date Jan 13, 2009
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for transferring data on a data link
- Patent number 7,296,211
- Issue date Nov 13, 2007
- Lockheed Martin Corporation
- Robert M. Cole
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for dynamic modification of microprocessor ins...
- Patent number 7,254,697
- Issue date Aug 7, 2007
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for forward error correction
- Patent number 7,076,724
- Issue date Jul 11, 2006
- Lockheed Martin Corporation
- Robert M. Cole
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable timing circuit for testing the cycle time of functiona...
- Patent number 6,415,402
- Issue date Jul 2, 2002
- International Business Machines Corporation
- James W. Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable timing circuit for testing the cycle time of functiona...
- Patent number 6,219,813
- Issue date Apr 17, 2001
- International Business Machines Corporation
- James W. Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level computer cache system providing plural cache controller...
- Patent number 5,809,525
- Issue date Sep 15, 1998
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error windowing for storage subsystem recovery
- Patent number 5,539,875
- Issue date Jul 23, 1996
- International Business Machines Corporation
- James W. Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical computer cache system
- Patent number 5,539,895
- Issue date Jul 23, 1996
- International Business Machines Corporation
- James W. Bishop
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CONSTRAINED CARRIES ON SPECULATIVE COUNTERS
- Publication number 20230004396
- Publication date Jan 5, 2023
- International Business Machines Corporation
- Dan Buerkle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SAVING AND RESTORING A TRANSACTION MEMORY STATE
- Publication number 20200301758
- Publication date Sep 24, 2020
- International Business Machines Corporation
- Steven J. BATTLE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING A HARDWARE LEVEL...
- Publication number 20190213055
- Publication date Jul 11, 2019
- International Business Machines Corporation
- BRIAN D. BARRICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COLLISION AVOIDANCE SYSTEMS
- Publication number 20180122249
- Publication date May 3, 2018
- Lockheed Martin Corporation
- John C. CECCHERELLI
- G01 - MEASURING TESTING
Information Patent Application
ECC SCRUBBING METHOD IN A MULTI-SLICE MICROPROCESSOR
- Publication number 20180095820
- Publication date Apr 5, 2018
- International Business Machines Corporation
- Brian D. BARRICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ECC SCRUBBING IN A MULTI-SLICE MICROPROCESSOR
- Publication number 20170351568
- Publication date Dec 7, 2017
- International Business Machines Corporation
- Brian D. BARRICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING A HARDWARE LEVEL...
- Publication number 20170286183
- Publication date Oct 5, 2017
- International Business Machines Corporation
- BRIAN D. BARRICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-PIPE ERROR SCRUBBING WITHIN A PROCESSOR CORE
- Publication number 20170286202
- Publication date Oct 5, 2017
- International Business Machines Corporation
- BRIAN D. BARRICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD MIGRATION USING A MICROCODE ENGINE OF A MULTI-SLICE PROCESSOR
- Publication number 20170262281
- Publication date Sep 14, 2017
- International Business Machines Corporation
- JAMES W. BISHOP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENSOR ARRAY PACKAGING SOLUTION
- Publication number 20160178410
- Publication date Jun 23, 2016
- Lockheed Martin Corporation
- James E. BISHOP
- G01 - MEASURING TESTING
Information Patent Application
Region-Weighted Accounting of Multi-Threaded Processor Core Accordi...
- Publication number 20140053164
- Publication date Feb 20, 2014
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor Including Age Tracking of Issue Queue Instructions
- Publication number 20120260069
- Publication date Oct 11, 2012
- IBM Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Region-Weighted Accounting of Multi-Threaded Processor Core Accordi...
- Publication number 20120246447
- Publication date Sep 27, 2012
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR INCLUDING AGE TRACKING OF ISSUE QUEUE INSTRUCTIONS
- Publication number 20110185159
- Publication date Jul 28, 2011
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selective Execution Dependency Matrix
- Publication number 20100257341
- Publication date Oct 7, 2010
- International Business Machines Corporation
- Mary D. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selecting Fixed-Point Instructions to Issue on Load-Store Unit
- Publication number 20100250901
- Publication date Sep 30, 2010
- International Business Machines Corporation
- Christopher Michael Abernathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INFORMATION HANDLING SYSTEM INCLUDING A PROCESSOR WITH A BIFURCATED...
- Publication number 20100161942
- Publication date Jun 24, 2010
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Implementing a Hardware-Supported Thread Assi...
- Publication number 20090106538
- Publication date Apr 23, 2009
- James W. Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thread Priority Method for Ensuring Processing Fairness in Simultan...
- Publication number 20080294884
- Publication date Nov 27, 2008
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods to randomly or pseudo-randomly, without bias, select instru...
- Publication number 20060184776
- Publication date Aug 17, 2006
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of implementing precise, localized hardware-error workaround...
- Publication number 20060184770
- Publication date Aug 17, 2006
- International Business Machines Corporation
- James W. Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thread priority method, apparatus, and computer program product for...
- Publication number 20060184946
- Publication date Aug 17, 2006
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for dynamic modification of microprocessor ins...
- Publication number 20060184768
- Publication date Aug 17, 2006
- International Business Machines Corporation
- James W. Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for checkpointing instruction groups with out-of-order float...
- Publication number 20060179346
- Publication date Aug 10, 2006
- International Business Machines Corporation
- James Wilson Bishop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for transferring data on a data link
- Publication number 20030237041
- Publication date Dec 25, 2003
- Robert M. Cole
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for forward error correction
- Publication number 20030237038
- Publication date Dec 25, 2003
- Robert M. Cole
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable timing circuit for testing the cycle time of functiona...
- Publication number 20010013111
- Publication date Aug 9, 2001
- International Business Machines Corporation
- James W. Bishop
- G01 - MEASURING TESTING

James W. Bishop

Person

Patents Grantslast 30 patents

Constrained carries on speculative counters

Operation of a multi-slice processor implementing a hardware level...

Saving and restoring a transaction memory state

Thread migration using a microcode engine of a multi-slice processor

Operation of a multi-slice processor implementing a hardware level...

ECC scrubbing method in a multi-slice microprocessor

In-pipe error scrubbing within a processor core

ECC scrubbing in a multi-slice microprocessor

Sensor array packaging solution

Region-weighted accounting of multi-threaded processor core accordi...

Region-weighted accounting of multi-threaded processor core accordi...

Processor including age tracking of issue queue instructions

Thread priority method for ensuring processing fairness in simultan...

Processor including age tracking of issue queue instructions

Selecting fixed-point instructions to issue on load-store unit

Information handling system including a processor with a bifurcated...

System and method for implementing a hardware-supported thread assi...

Thread priority method for ensuring processing fairness in simultan...

Methods to randomly or pseudo-randomly, without bias, select instru...

Method for checkpointing instruction groups with out-of-order float...

System and method for transferring data on a data link

Method and apparatus for dynamic modification of microprocessor ins...

System and method for forward error correction

Programmable timing circuit for testing the cycle time of functiona...

Programmable timing circuit for testing the cycle time of functiona...

Multi-level computer cache system providing plural cache controller...

Error windowing for storage subsystem recovery

Hierarchical computer cache system

Patents Applicationslast 30 patents

CONSTRAINED CARRIES ON SPECULATIVE COUNTERS

SAVING AND RESTORING A TRANSACTION MEMORY STATE

OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING A HARDWARE LEVEL...

COLLISION AVOIDANCE SYSTEMS

ECC SCRUBBING METHOD IN A MULTI-SLICE MICROPROCESSOR

ECC SCRUBBING IN A MULTI-SLICE MICROPROCESSOR

OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING A HARDWARE LEVEL...

IN-PIPE ERROR SCRUBBING WITHIN A PROCESSOR CORE

THREAD MIGRATION USING A MICROCODE ENGINE OF A MULTI-SLICE PROCESSOR

SENSOR ARRAY PACKAGING SOLUTION

Region-Weighted Accounting of Multi-Threaded Processor Core Accordi...

Processor Including Age Tracking of Issue Queue Instructions

Region-Weighted Accounting of Multi-Threaded Processor Core Accordi...

PROCESSOR INCLUDING AGE TRACKING OF ISSUE QUEUE INSTRUCTIONS

Selective Execution Dependency Matrix

Selecting Fixed-Point Instructions to Issue on Load-Store Unit

INFORMATION HANDLING SYSTEM INCLUDING A PROCESSOR WITH A BIFURCATED...

System and Method for Implementing a Hardware-Supported Thread Assi...

Thread Priority Method for Ensuring Processing Fairness in Simultan...

Methods to randomly or pseudo-randomly, without bias, select instru...

Method of implementing precise, localized hardware-error workaround...

Thread priority method, apparatus, and computer program product for...

Method and apparatus for dynamic modification of microprocessor ins...

Method for checkpointing instruction groups with out-of-order float...

System and method for transferring data on a data link

System and method for forward error correction

Programmable timing circuit for testing the cycle time of functiona...