James W. Blatchford, JR.

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
SRAM layout for double patterning
- Patent number 11,974,421
- Issue date Apr 30, 2024
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM layout for double patterning
- Patent number 10,840,250
- Issue date Nov 17, 2020
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Rectangular via for ensuring via yield in the absence of via redund...
- Patent number 10,741,489
- Issue date Aug 11, 2020
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM layout for double patterning
- Patent number 10,181,474
- Issue date Jan 15, 2019
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM layout for double patterning
- Patent number 10,103,153
- Issue date Oct 16, 2018
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal on elongated contacts
- Patent number 10,103,171
- Issue date Oct 16, 2018
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Elongated contacts using litho-freeze-litho-etch process
- Patent number 10,043,714
- Issue date Aug 7, 2018
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form silicide and contact at embedded epitaxial facet
- Patent number 10,008,499
- Issue date Jun 26, 2018
- Texas Instruments Incorporated
- Kwan-Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a transistor with an active area layout having bo...
- Patent number 9,899,364
- Issue date Feb 20, 2018
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form silicide and contact at embedded epitaxial facet
- Patent number 9,812,452
- Issue date Nov 7, 2017
- Texas Instruments Incorporated
- Kwan-Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Elongated contacts using litho-freeze-litho-etch process
- Patent number 9,620,419
- Issue date Apr 11, 2017
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form silicide and contact at embedded epitaxial facet
- Patent number 9,508,601
- Issue date Nov 29, 2016
- Texas Instruments Incorporated
- Kwan-Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal on elongated contacts
- Patent number 9,312,170
- Issue date Apr 12, 2016
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Elongated contacts using litho-freeze-litho-etch process
- Patent number 9,305,848
- Issue date Apr 5, 2016
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Raised source/drain MOS transistor and method of forming the transi...
- Patent number 9,178,038
- Issue date Nov 3, 2015
- Texas Instruments Incorporated
- Seung-Chul Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout method to minimize context effects and die area
- Patent number 9,123,562
- Issue date Sep 1, 2015
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for ensuring DPT compliance for auto-routed via layers
- Patent number 9,112,000
- Issue date Aug 18, 2015
- Texas Instruments Incorporated
- James Walter Blatchford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-track cross-connect in double-patterned structure using rectang...
- Patent number 9,024,450
- Issue date May 5, 2015
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System for controlling SiGe-to-gate spacing
- Patent number 8,828,833
- Issue date Sep 9, 2014
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to ensure double patterning technology compliance in standar...
- Patent number 8,756,550
- Issue date Jun 17, 2014
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for generating ultra-short-run-length dummy poly features
- Patent number 8,751,977
- Issue date Jun 10, 2014
- Texas Instruments Incorporated
- James Walter Blatchford
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Perturbational technique for co-optimizing design rules and illumin...
- Patent number 8,745,548
- Issue date Jun 3, 2014
- Texas Instruments Incorporated
- James Walter Blatchford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for ensuring DPT compliance with autorouted metal layers
- Patent number 8,707,223
- Issue date Apr 22, 2014
- Texas Instruments Incorporated
- James Walter Blatchford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control of local environment for polysilicon conductors in integrat...
- Patent number 8,703,608
- Issue date Apr 22, 2014
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate CD control using local design on both sides of neighboring dum...
- Patent number 8,663,879
- Issue date Mar 4, 2014
- Texas Instruments Incorporated
- James Walter Blatchford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate CD control using local design on both sides of neighboring dum...
- Patent number 8,667,432
- Issue date Mar 4, 2014
- Texas Instrument Incorporated
- James Walter Blatchford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Perturbational technique for co-optimizing design rules and illumin...
- Patent number 8,607,170
- Issue date Dec 10, 2013
- Texas Instruments Incorporated
- James Walter Blatchford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual alignment strategy for optimizing contact layer alignment
- Patent number 8,603,905
- Issue date Dec 10, 2013
- Texas Instruments Incorporated
- James Walter Blatchford
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Manufacturability enhancements for gate patterning process using po...
- Patent number 8,584,053
- Issue date Nov 12, 2013
- Texas Intruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-track cross-connect in double-patterned structure using rectang...
- Patent number 8,580,675
- Issue date Nov 12, 2013
- Texas Instruments Incorporated
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SRAM LAYOUT FOR DOUBLE PATTERNING
- Publication number 20210028179
- Publication date Jan 28, 2021
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SRAM LAYOUT FOR DOUBLE PATTERNING
- Publication number 20190109143
- Publication date Apr 11, 2019
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET
- Publication number 20180047728
- Publication date Feb 15, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Kwan-Yong LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS
- Publication number 20170178966
- Publication date Jun 22, 2017
- TEXAS INSTRUMENTS INCORPORATED
- James Walter BLATCHFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET
- Publication number 20170047329
- Publication date Feb 16, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Kwan-Yong LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL ON ELONGATED CONTACTS
- Publication number 20160190156
- Publication date Jun 30, 2016
- TEXAS INSTRUMENTS INCORPORATED
- James Walter BLATCHFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS
- Publication number 20160190016
- Publication date Jun 30, 2016
- TEXAS INSTRUMENTS INCORPORATED
- James Walter BLATCHFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SRAM LAYOUT FOR DOUBLE PATTERNING
- Publication number 20160020214
- Publication date Jan 21, 2016
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYOUT METHOD TO MINIMIZE CONTEXT EFFECTS AND DIE AREA
- Publication number 20150332974
- Publication date Nov 19, 2015
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET
- Publication number 20150170972
- Publication date Jun 18, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Kwan-Yong LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS
- Publication number 20150170975
- Publication date Jun 18, 2015
- TEXAS INSTRUMENTS INCORPORATED
- James Walter BLATCHFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL ON ELONGATED CONTACTS
- Publication number 20150170962
- Publication date Jun 18, 2015
- TEXAS INSTRUMENTS INCORPORATED
- James Walter BLATCHFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RAISED SOURCE/DRAIN MOS TRANSISTOR AND METHOD OF FORMING THE TRANSI...
- Publication number 20150140769
- Publication date May 21, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Seung-Chul Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Raised Source/Drain MOS Transistor and Method of Forming the Transi...
- Publication number 20140183663
- Publication date Jul 3, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Seung-Chul Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PERTURBATIONAL TECHNIQUE FOR CO-OPTIMIZING DESIGN RULES AND ILLUMIN...
- Publication number 20140101622
- Publication date Apr 10, 2014
- James Walter BLATCHFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANG...
- Publication number 20140035160
- Publication date Feb 6, 2014
- TEXAS INSTRUMENTS INCORPORATED
- James Walter BLATCHFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTROL OF LOCAL ENVIRONMENT FOR POLYSILICON CONDUCTORS IN INTEGRAT...
- Publication number 20130316505
- Publication date Nov 28, 2013
- TEXAS INSTRUMENTS INCORPORATED
- James Walter BLATCHFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUM...
- Publication number 20130246983
- Publication date Sep 19, 2013
- TEXAS INSTRUMENTS INCORPORATED
- James Walter BLATCHFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUM...
- Publication number 20130244144
- Publication date Sep 19, 2013
- TEXAS INSTRUMENTS INCORPORATED
- James Walter BLATCHFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR ENSURING DPT COMPLIANCE WITH AUTOROUTED METAL LAYERS
- Publication number 20130074028
- Publication date Mar 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- James Walter BLATCHFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM LAYOUT FOR DOUBLE PATTERNING
- Publication number 20130069168
- Publication date Mar 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method For Ensuring DPT Compliance for Auto-Routed Via Layers
- Publication number 20130072020
- Publication date Mar 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ILLUMINATION AND DESIGN RULE METHOD FOR DOUBLE PATTERNED SLOTTED CO...
- Publication number 20130069170
- Publication date Mar 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECTANGULAR VIA FOR ENSURING VIA YIELD IN THE ABSENCE OF VIA REDUND...
- Publication number 20130069244
- Publication date Mar 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layout Method To Minimize Context Effects and Die Area
- Publication number 20130069081
- Publication date Mar 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method To Ensure Double Patterning Technology Compliance In Standar...
- Publication number 20130074029
- Publication date Mar 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MANUFACTURABILITY ENHANCEMENTS FOR GATE PATTERNING PROCESS USING PO...
- Publication number 20120331425
- Publication date Dec 27, 2012
- James Walter Blatchford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID PITCH-SPLIT PATTERN-SPLIT LITHOGRAPHY PROCESS
- Publication number 20120225550
- Publication date Sep 6, 2012
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
PERTURBATIONAL TECHNIQUE FOR CO-OPTIMIZING DESIGN RULES AND ILLUMIN...
- Publication number 20120227015
- Publication date Sep 6, 2012
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PATTERN-SPLIT DECOMPOSITION STRATEGY FOR DOUBLE-PATTERNED LITHOGRAP...
- Publication number 20120225551
- Publication date Sep 6, 2012
- TEXAS INSTRUMENTS INCORPORATED
- James Walter Blatchford
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

James W. Blatchford, JR.

Person

Patents Grantslast 30 patents

SRAM layout for double patterning

SRAM layout for double patterning

Rectangular via for ensuring via yield in the absence of via redund...

SRAM layout for double patterning

SRAM layout for double patterning

Metal on elongated contacts

Elongated contacts using litho-freeze-litho-etch process

Method to form silicide and contact at embedded epitaxial facet

Method of forming a transistor with an active area layout having bo...

Method to form silicide and contact at embedded epitaxial facet

Elongated contacts using litho-freeze-litho-etch process

Method to form silicide and contact at embedded epitaxial facet

Metal on elongated contacts

Elongated contacts using litho-freeze-litho-etch process

Raised source/drain MOS transistor and method of forming the transi...

Layout method to minimize context effects and die area

Method for ensuring DPT compliance for auto-routed via layers

Two-track cross-connect in double-patterned structure using rectang...

System for controlling SiGe-to-gate spacing

Method to ensure double patterning technology compliance in standar...

Method for generating ultra-short-run-length dummy poly features

Perturbational technique for co-optimizing design rules and illumin...

Method for ensuring DPT compliance with autorouted metal layers

Control of local environment for polysilicon conductors in integrat...

Gate CD control using local design on both sides of neighboring dum...

Gate CD control using local design on both sides of neighboring dum...

Perturbational technique for co-optimizing design rules and illumin...

Dual alignment strategy for optimizing contact layer alignment

Manufacturability enhancements for gate patterning process using po...

Two-track cross-connect in double-patterned structure using rectang...

Patents Applicationslast 30 patents

SRAM LAYOUT FOR DOUBLE PATTERNING

SRAM LAYOUT FOR DOUBLE PATTERNING

METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET

ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS

METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET

METAL ON ELONGATED CONTACTS

ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS

SRAM LAYOUT FOR DOUBLE PATTERNING

LAYOUT METHOD TO MINIMIZE CONTEXT EFFECTS AND DIE AREA

METHOD TO FORM SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET

ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS

METAL ON ELONGATED CONTACTS

RAISED SOURCE/DRAIN MOS TRANSISTOR AND METHOD OF FORMING THE TRANSI...

Raised Source/Drain MOS Transistor and Method of Forming the Transi...

PERTURBATIONAL TECHNIQUE FOR CO-OPTIMIZING DESIGN RULES AND ILLUMIN...

TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANG...

CONTROL OF LOCAL ENVIRONMENT FOR POLYSILICON CONDUCTORS IN INTEGRAT...

GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUM...

GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUM...

METHOD FOR ENSURING DPT COMPLIANCE WITH AUTOROUTED METAL LAYERS

SRAM LAYOUT FOR DOUBLE PATTERNING

Method For Ensuring DPT Compliance for Auto-Routed Via Layers

ILLUMINATION AND DESIGN RULE METHOD FOR DOUBLE PATTERNED SLOTTED CO...

RECTANGULAR VIA FOR ENSURING VIA YIELD IN THE ABSENCE OF VIA REDUND...

Layout Method To Minimize Context Effects and Die Area

Method To Ensure Double Patterning Technology Compliance In Standar...

MANUFACTURABILITY ENHANCEMENTS FOR GATE PATTERNING PROCESS USING PO...

HYBRID PITCH-SPLIT PATTERN-SPLIT LITHOGRAPHY PROCESS

PERTURBATIONAL TECHNIQUE FOR CO-OPTIMIZING DESIGN RULES AND ILLUMIN...

PATTERN-SPLIT DECOMPOSITION STRATEGY FOR DOUBLE-PATTERNED LITHOGRAP...