James W. Keeley

Person

Nashua, NH, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for providing more effective reiterations of i...
- Patent number 5,664,200
- Issue date Sep 2, 1997
- Bull HN Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-board diagnostic testing
- Patent number 5,548,713
- Issue date Aug 20, 1996
- Bull HN Information Systems Inc.
- Keith L. Petry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-on sequencing apparatus for initializing and testing a system...
- Patent number 5,491,790
- Issue date Feb 13, 1996
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus interface state machines with independent access to memory, pro...
- Patent number 5,471,638
- Issue date Nov 28, 1995
- Bull HN Inforamtion Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable system bus priority network
- Patent number 5,446,847
- Issue date Aug 29, 1995
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for providing more effective reiterations of p...
- Patent number 5,404,535
- Issue date Apr 4, 1995
- Bull HN Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system having a bus command generated by one subsys...
- Patent number 5,379,378
- Issue date Jan 3, 1995
- Bull HN Information Systems Inc.
- Arthur Peters
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Means for providing a graceful power shut-down capability in a mult...
- Patent number 5,367,697
- Issue date Nov 22, 1994
- Bull HN Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor bus access
- Patent number 5,341,501
- Issue date Aug 23, 1994
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing unit having multiple synchronous bus for sharing access...
- Patent number 5,341,508
- Issue date Aug 23, 1994
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus controller having state machine for translating commands and co...
- Patent number 5,341,495
- Issue date Aug 23, 1994
- Bull HN Information Systems, Inc.
- Thomas F. Joyce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor bus interface protocol analyzer
- Patent number 5,293,384
- Issue date Mar 8, 1994
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for avoiding processor deadly embrace in a mul...
- Patent number 5,283,870
- Issue date Feb 1, 1994
- Bull HN Information Systems Inc.
- Thomas F. Joyce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor system with centralized initialization, testing and...
- Patent number 5,274,797
- Issue date Dec 28, 1993
- Bull HN Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing health tests of units of a data...
- Patent number 5,210,757
- Issue date May 11, 1993
- Bull HN Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recovery method and apparatus for a pipelined processing unit of a...
- Patent number 5,193,181
- Issue date Mar 9, 1993
- Bull HN Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for loading and verifying a control store memory of a cen...
- Patent number 4,910,666
- Issue date Mar 20, 1990
- Bull HN Information Systems Inc.
- Chester M. Nibby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system with a fast interrupt
- Patent number 4,839,800
- Issue date Jun 13, 1989
- Bull HN Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache resiliency in processing a variety of address faults
- Patent number 4,833,601
- Issue date May 23, 1989
- Bull HN Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor level change synchronization apparatus
- Patent number 4,802,087
- Issue date Jan 31, 1989
- Honeywell Bull Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address transform method and apparatus for transferring addresses
- Patent number 4,799,222
- Issue date Jan 17, 1989
- Honeywell Bull Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor coherent cache system including two level shared cac...
- Patent number 4,785,395
- Issue date Nov 15, 1988
- Honeywell Bull Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read in process memory apparatus
- Patent number 4,768,148
- Issue date Aug 30, 1988
- Honeywell Bull Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resilient bus system
- Patent number 4,764,862
- Issue date Aug 16, 1988
- Honeywell Bull Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resilient bus system
- Patent number 4,763,243
- Issue date Aug 9, 1988
- Honeywell Bull Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Channel number priority assignment apparatus
- Patent number 4,724,519
- Issue date Feb 9, 1988
- Honeywell Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor shared pipeline cache memory with split cycle and co...
- Patent number 4,695,943
- Issue date Sep 22, 1987
- Honeywell Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test apparatus for testing a multilevel cache system with graceful...
- Patent number 4,686,621
- Issue date Aug 11, 1987
- Honeywell Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enable/disable control checking apparatus
- Patent number 4,667,288
- Issue date May 19, 1987
- Honeywell Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared interface apparatus for testing the memory sections of a cac...
- Patent number 4,575,792
- Issue date Mar 11, 1986
- Honeywell Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING

James W. Keeley

Person

Patents Grantslast 30 patents

Apparatus and method for providing more effective reiterations of i...

On-board diagnostic testing

Power-on sequencing apparatus for initializing and testing a system...

Bus interface state machines with independent access to memory, pro...

Programmable system bus priority network

Apparatus and method for providing more effective reiterations of p...

Data processing system having a bus command generated by one subsys...

Means for providing a graceful power shut-down capability in a mult...

Processor bus access

Processing unit having multiple synchronous bus for sharing access...

Bus controller having state machine for translating commands and co...

Microprocessor bus interface protocol analyzer

Method and apparatus for avoiding processor deadly embrace in a mul...

Multiprocessor system with centralized initialization, testing and...

Method and apparatus for performing health tests of units of a data...

Recovery method and apparatus for a pipelined processing unit of a...

Apparatus for loading and verifying a control store memory of a cen...

Data processing system with a fast interrupt

Cache resiliency in processing a variety of address faults

Multiprocessor level change synchronization apparatus

Address transform method and apparatus for transferring addresses

Multiprocessor coherent cache system including two level shared cac...

Read in process memory apparatus

Resilient bus system

Resilient bus system

Channel number priority assignment apparatus

Multiprocessor shared pipeline cache memory with split cycle and co...

Test apparatus for testing a multilevel cache system with graceful...

Enable/disable control checking apparatus

Shared interface apparatus for testing the memory sections of a cac...