Jan Gray

Person

Bellevue, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Composing diverse remote cores and FPGAs
- Patent number 11,973,697
- Issue date Apr 30, 2024
- Gray Research LLC
- Jan Stephen Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction block allocation
- Patent number 11,755,484
- Issue date Sep 12, 2023
- Microsoft Technology Licensing, LLC
- Jan S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Out-of-order block-based processors and instruction schedulers usin...
- Patent number 11,687,345
- Issue date Jun 27, 2023
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA-efficient directional two-dimensional router
- Patent number 11,677,662
- Issue date Jun 13, 2023
- Gray Research LLC
- Jan Stephen Gray
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multiported parity scoreboard circuit
- Patent number 11,455,171
- Issue date Sep 27, 2022
- Gray Research LLC
- Jan Stephen Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid block-based processor and custom function blocks
- Patent number 11,449,342
- Issue date Sep 20, 2022
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shortcut routing on segmented directional torus interconnection net...
- Patent number 11,223,573
- Issue date Jan 11, 2022
- Gray Research LLC
- Jan Stephen Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental scheduler for out-of-order block ISA processors
- Patent number 11,106,467
- Issue date Aug 31, 2021
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoupled processor instruction window and operand buffer
- Patent number 11,048,517
- Issue date Jun 29, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicast message delivery using a directional two-dimensional rout...
- Patent number 10,911,352
- Issue date Feb 2, 2021
- Gray Research LLC
- Jan Stephen Gray
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Composing cores and FPGAS at massive scale with directional, two di...
- Patent number 10,587,534
- Issue date Mar 10, 2020
- Gray Research LLC
- Jan Stephen Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Connecting diverse client cores using a directional two-dimensional...
- Patent number 10,419,338
- Issue date Sep 17, 2019
- Gray Research LLC
- Jan Stephen Gray
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Decoding information about a group of instructions including a size...
- Patent number 10,409,599
- Issue date Sep 10, 2019
- Microsoft Technology Licensing, LLC
- Jan Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying branch targets
- Patent number 10,409,606
- Issue date Sep 10, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoupled processor instruction window and operand buffer
- Patent number 10,346,168
- Issue date Jul 9, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel decision tree processor architecture
- Patent number 10,332,008
- Issue date Jun 25, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Explicit instruction scheduler state information for a processor
- Patent number 10,175,988
- Issue date Jan 8, 2019
- Microsoft Technology Licensing, LLC
- Jan Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Directional two-dimensional router and interconnection network for...
- Patent number 10,116,557
- Issue date Oct 30, 2018
- Gray Research LLC
- Jan Stephen Gray
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mapping instruction blocks based on block size
- Patent number 9,952,867
- Issue date Apr 24, 2018
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Age-based management of instruction blocks in a processor instructi...
- Patent number 9,946,548
- Issue date Apr 17, 2018
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Private memory regions and coherency optimization by controlling sn...
- Patent number 9,767,027
- Issue date Sep 19, 2017
- Microsoft Technology Licensing, LLC
- Jan Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bulk allocation of instruction blocks to a processor instruction wi...
- Patent number 9,720,693
- Issue date Aug 1, 2017
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient garbage collection and exception handling in a hardware a...
- Patent number 9,658,880
- Issue date May 23, 2017
- Microsoft Technology Licensing, LLC
- Jan Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling operating system (OS) transitions in an unbounded transact...
- Patent number 9,477,515
- Issue date Oct 25, 2016
- Intel Corporation
- Koichi Yamada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using buffered stores or monitoring to filter redundant transaction...
- Patent number 9,280,397
- Issue date Mar 8, 2016
- Intel Corporation
- Ali-Reza Adl-Tabatabai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanisms to accelerate transactions using buffered stores
- Patent number 9,195,600
- Issue date Nov 24, 2015
- Intel Corporation
- Ali-Reza Adl-Tabatabai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instrumentation of hardware assisted transactional memory system
- Patent number 9,092,253
- Issue date Jul 28, 2015
- Microsoft Technology Licensing, LLC
- Martin Taillefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanisms to accelerate transactions using buffered stores
- Patent number 9,069,670
- Issue date Jun 30, 2015
- Intel Corporation
- Ali-Reza Adl-Tabatabai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated method and system for collecting and reporting API perfor...
- Patent number 9,027,000
- Issue date May 5, 2015
- Microsoft Technology Licensing, LLC
- Nicholas Guerrera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache metadata for accelerating software transactional memory
- Patent number 8,898,652
- Issue date Nov 25, 2014
- Microsoft Corporation
- Jan Gray
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTICAST MESSAGE DELIVERY ACROSS REMOTE CORES
- Publication number 20240223514
- Publication date Jul 4, 2024
- Gray Research LLC
- Jan Stephen Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPOSING DIVERSE REMOTE CORES AND FPGAS
- Publication number 20220417177
- Publication date Dec 29, 2022
- Gray Research LLC
- Jan Stephen Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FPGA-EFFICIENT DIRECTIONAL TWO-DIMENSIONAL ROUTER
- Publication number 20210160177
- Publication date May 27, 2021
- Gray Research LLC
- Jan Stephen GRAY
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTIPORTED PARITY SCOREBOARD CIRCUIT
- Publication number 20210117201
- Publication date Apr 22, 2021
- Gray Research LLC
- Jan Stephen Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICAST MESSAGE DELIVERY USING A DIRECTIONAL TWO-DIMENSIONAL ROUT...
- Publication number 20200259743
- Publication date Aug 13, 2020
- Gray Research LLC
- Jan Stephen GRAY
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SHORTCUT ROUTING ON SEGMENTED DIRECTIONAL TORUS INTERCONNECTION NET...
- Publication number 20200213245
- Publication date Jul 2, 2020
- Gray Research LLC
- Jan Stephen Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECOUPLED PROCESSOR INSTRUCTION WINDOW AND OPERAND BUFFER
- Publication number 20190310852
- Publication date Oct 10, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONNECTING DIVERSE CLIENT CORES USING A DIRECTIONAL TWO-DIMENSIONAL...
- Publication number 20190028387
- Publication date Jan 24, 2019
- Gray Research LLC
- Jan Stephen GRAY
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
COMPOSING CORES AND FPGAS AT MASSIVE SCALE WITH DIRECTIONAL, TWO DI...
- Publication number 20180287964
- Publication date Oct 4, 2018
- Gray Research LLC
- Jan Stephen Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTIONAL REGISTER FILE FOR A PROCESSOR
- Publication number 20180032335
- Publication date Feb 1, 2018
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUT-OF-ORDER BLOCK-BASED PROCESSOR
- Publication number 20180032344
- Publication date Feb 1, 2018
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD-STORE QUEUE FOR BLOCK-BASED PROCESSOR
- Publication number 20170371659
- Publication date Dec 28, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD-STORE QUEUE FOR MULTIPLE PROCESSOR CORES
- Publication number 20170371660
- Publication date Dec 28, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL INSTRUCTION SCHEDULER FOR BLOCK ISA PROCESSOR
- Publication number 20170315812
- Publication date Nov 2, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUT-OF-ORDER BLOCK-BASED PROCESSORS AND INSTRUCTION SCHEDULERS
- Publication number 20170315814
- Publication date Nov 2, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREMENTAL SCHEDULER FOR OUT-OF-ORDER BLOCK ISA PROCESSORS
- Publication number 20170315813
- Publication date Nov 2, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID BLOCK-BASED PROCESSOR AND CUSTOM FUNCTION BLOCKS
- Publication number 20170315815
- Publication date Nov 2, 2017
- Microsoft Technology Licensing, LLC
- Aaron L. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MASSIVELY PARALLEL COMPUTER, ACCELERATED COMPUTING CLUSTERS, AND TW...
- Publication number 20170220499
- Publication date Aug 3, 2017
- Gray Research LLC
- Jan Stephen Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS TO TARGET ADDRESS
- Publication number 20160378488
- Publication date Dec 29, 2016
- Microsoft Technology Licensing, LLC
- Douglas Christopher Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFYING BRANCH TARGETS
- Publication number 20160378499
- Publication date Dec 29, 2016
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION BLOCK ALLOCATION
- Publication number 20160378661
- Publication date Dec 29, 2016
- Microsoft Technology Licensing, LLC
- Jan S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECOUPLED PROCESSOR INSTRUCTION WINDOW AND OPERAND BUFFER
- Publication number 20160378479
- Publication date Dec 29, 2016
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGE-BASED MANAGEMENT OF INSTRUCTION BLOCKS IN A PROCESSOR INSTRUCTI...
- Publication number 20160378502
- Publication date Dec 29, 2016
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Decoding Information About a Group of Instructions Including a Size...
- Publication number 20160378492
- Publication date Dec 29, 2016
- Microsoft Technology Licensing, LLC
- Jan Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAPPING INSTRUCTION BLOCKS BASED ON BLOCK SIZE
- Publication number 20160378484
- Publication date Dec 29, 2016
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINATION OF TARGET LOCATION FOR TRANSFER OF PROCESSOR CONTROL
- Publication number 20160378491
- Publication date Dec 29, 2016
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BULK ALLOCATION OF INSTRUCTION BLOCKS TO A PROCESSOR INSTRUCTION WI...
- Publication number 20160378493
- Publication date Dec 29, 2016
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Explicit Instruction Scheduler State Information for a Processor
- Publication number 20160378496
- Publication date Dec 29, 2016
- Microsoft Technology Licensing, LLC
- Jan Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECTIONAL TWO-DIMENSIONAL ROUTER AND INTERCONNECTION NETWORK FOR...
- Publication number 20160344629
- Publication date Nov 24, 2016
- Gray Research LLC
- Jan Stephen GRAY
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Providing Services in a System having a Hardware Acceleration Plane...
- Publication number 20160308649
- Publication date Oct 20, 2016
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Person

Patents Grantslast 30 patents

Composing diverse remote cores and FPGAs

Instruction block allocation

Out-of-order block-based processors and instruction schedulers usin...

FPGA-efficient directional two-dimensional router

Multiported parity scoreboard circuit

Hybrid block-based processor and custom function blocks

Shortcut routing on segmented directional torus interconnection net...

Incremental scheduler for out-of-order block ISA processors

Decoupled processor instruction window and operand buffer

Multicast message delivery using a directional two-dimensional rout...

Composing cores and FPGAS at massive scale with directional, two di...

Connecting diverse client cores using a directional two-dimensional...

Decoding information about a group of instructions including a size...

Verifying branch targets

Decoupled processor instruction window and operand buffer

Parallel decision tree processor architecture

Explicit instruction scheduler state information for a processor

Directional two-dimensional router and interconnection network for...

Mapping instruction blocks based on block size

Age-based management of instruction blocks in a processor instructi...

Private memory regions and coherency optimization by controlling sn...

Bulk allocation of instruction blocks to a processor instruction wi...

Efficient garbage collection and exception handling in a hardware a...

Handling operating system (OS) transitions in an unbounded transact...

Using buffered stores or monitoring to filter redundant transaction...

Mechanisms to accelerate transactions using buffered stores

Instrumentation of hardware assisted transactional memory system

Mechanisms to accelerate transactions using buffered stores

Automated method and system for collecting and reporting API perfor...

Cache metadata for accelerating software transactional memory

Patents Applicationslast 30 patents

MULTICAST MESSAGE DELIVERY ACROSS REMOTE CORES

COMPOSING DIVERSE REMOTE CORES AND FPGAS

FPGA-EFFICIENT DIRECTIONAL TWO-DIMENSIONAL ROUTER

MULTIPORTED PARITY SCOREBOARD CIRCUIT

MULTICAST MESSAGE DELIVERY USING A DIRECTIONAL TWO-DIMENSIONAL ROUT...

SHORTCUT ROUTING ON SEGMENTED DIRECTIONAL TORUS INTERCONNECTION NET...

DECOUPLED PROCESSOR INSTRUCTION WINDOW AND OPERAND BUFFER

CONNECTING DIVERSE CLIENT CORES USING A DIRECTIONAL TWO-DIMENSIONAL...

COMPOSING CORES AND FPGAS AT MASSIVE SCALE WITH DIRECTIONAL, TWO DI...

TRANSACTIONAL REGISTER FILE FOR A PROCESSOR

OUT-OF-ORDER BLOCK-BASED PROCESSOR

LOAD-STORE QUEUE FOR BLOCK-BASED PROCESSOR

LOAD-STORE QUEUE FOR MULTIPLE PROCESSOR CORES

PARALLEL INSTRUCTION SCHEDULER FOR BLOCK ISA PROCESSOR

OUT-OF-ORDER BLOCK-BASED PROCESSORS AND INSTRUCTION SCHEDULERS

INCREMENTAL SCHEDULER FOR OUT-OF-ORDER BLOCK ISA PROCESSORS

HYBRID BLOCK-BASED PROCESSOR AND CUSTOM FUNCTION BLOCKS

MASSIVELY PARALLEL COMPUTER, ACCELERATED COMPUTING CLUSTERS, AND TW...

ACCESS TO TARGET ADDRESS

VERIFYING BRANCH TARGETS

INSTRUCTION BLOCK ALLOCATION

DECOUPLED PROCESSOR INSTRUCTION WINDOW AND OPERAND BUFFER

AGE-BASED MANAGEMENT OF INSTRUCTION BLOCKS IN A PROCESSOR INSTRUCTI...

Decoding Information About a Group of Instructions Including a Size...

MAPPING INSTRUCTION BLOCKS BASED ON BLOCK SIZE

DETERMINATION OF TARGET LOCATION FOR TRANSFER OF PROCESSOR CONTROL

BULK ALLOCATION OF INSTRUCTION BLOCKS TO A PROCESSOR INSTRUCTION WI...

Explicit Instruction Scheduler State Information for a Processor

DIRECTIONAL TWO-DIMENSIONAL ROUTER AND INTERCONNECTION NETWORK FOR...

Providing Services in a System having a Hardware Acceleration Plane...