Jan Langer

Person

Chemnitz, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Device with data processing engine array that enables partial recon...
- Patent number 12,105,667
- Issue date Oct 1, 2024
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine arrangement in a device
- Patent number 11,972,132
- Issue date Apr 30, 2024
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communicating between data processing engines using shared memory
- Patent number 11,853,235
- Issue date Dec 26, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-addressing mode for DMA and non-sequential read and write pat...
- Patent number 11,669,464
- Issue date Jun 6, 2023
- Xilinx, Inc.
- Goran Hk Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device with data processing engine array that enables partial recon...
- Patent number 11,599,498
- Issue date Mar 7, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine arrangement in a device
- Patent number 11,573,726
- Issue date Feb 7, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event-based debug, trace, and profile in device with data processin...
- Patent number 11,567,881
- Issue date Jan 31, 2023
- Xilinx, Inc.
- Goran H. K. Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory tiles in data processing engine array
- Patent number 11,520,717
- Issue date Dec 6, 2022
- Xilinx, Inc.
- David Clarke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engines with cascade connected cores
- Patent number 11,443,091
- Issue date Sep 13, 2022
- Xilinx, Inc.
- Peter McColgan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communicating between data processing engines using shared memory
- Patent number 11,379,389
- Issue date Jul 5, 2022
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine tile architecture for an integrated circuit
- Patent number 11,372,803
- Issue date Jun 28, 2022
- Xilinx, Inc.
- Goran H. K. Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine array architecture with memory tiles
- Patent number 11,336,287
- Issue date May 17, 2022
- Xilinx, Inc.
- Javier Cabezas Rodriguez
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-port stream switch for stream interconnect network
- Patent number 11,323,391
- Issue date May 3, 2022
- Xilinx, Inc.
- Peter McColgan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine array architecture with memory tiles
- Patent number 11,296,707
- Issue date Apr 5, 2022
- Xilinx, Inc.
- Javier Cabezas Rodriguez
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual mode interconnect
- Patent number 11,113,223
- Issue date Sep 7, 2021
- Xilinx, Inc.
- Peter McColgan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data selection network for a data processing engine in an integrate...
- Patent number 11,061,673
- Issue date Jul 13, 2021
- Xilinx, Inc.
- Baris Ozgul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascade streaming between data processing engines in an array
- Patent number 11,016,822
- Issue date May 25, 2021
- Xilinx, Inc.
- Goran H. K. Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming interconnect architecture for data processing engine array
- Patent number 10,990,552
- Issue date Apr 27, 2021
- Xilinx, Inc.
- Goran Hk Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine arrangement in a device
- Patent number 10,866,753
- Issue date Dec 15, 2020
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device with data processing engine array that enables partial recon...
- Patent number 10,824,584
- Issue date Nov 3, 2020
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device with data processing engine array
- Patent number 10,747,690
- Issue date Aug 18, 2020
- Xilinx, Inc.
- Goran H K Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core for a data processing engine in an integrated circuit
- Patent number 10,747,531
- Issue date Aug 18, 2020
- Xilinx, Inc.
- Jan Langer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip interface architecture
- Patent number 10,635,622
- Issue date Apr 28, 2020
- Xilinx, Inc.
- Goran H. K. Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stall logic for a data processing engine in an integrated circuit
- Patent number 10,579,559
- Issue date Mar 3, 2020
- Xilinx, Inc.
- Goran H K Bilski
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DEVICE WITH DATA PROCESSING ENGINE ARRAY THAT ENABLES PARTIAL RECON...
- Publication number 20240256482
- Publication date Aug 1, 2024
- Xilinx, Inc.
- Juan J. NOGUERA SERRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE WITH DATA PROCESSING ENGINE ARRAY THAT ENABLES PARTIAL RECON...
- Publication number 20230205726
- Publication date Jun 29, 2023
- Xilinx, Inc.
- Juan J. NOGUERA SERRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
- Publication number 20230131698
- Publication date Apr 27, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATING BETWEEN DATA PROCESSING ENGINES USING SHARED MEMORY
- Publication number 20220283963
- Publication date Sep 8, 2022
- Xilinx, Inc.
- Juan J. NOGUERA SERRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING ENGINE TILE ARCHITECTURE FOR AN INTEGRATED CIRCUIT
- Publication number 20220283985
- Publication date Sep 8, 2022
- Xilinx, Inc.
- Goran Hk BILSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL MODE INTERCONNECT
- Publication number 20220015588
- Publication date Jan 20, 2022
- Xilinx, Inc.
- Peter MCCOLGAN
- A47 - FURNITURE DOMESTIC ARTICLES OR APPLIANCES COFFEE MILLS SPICE MILLS SUCT...
Information Patent Application
SYSTEM-ON-CHIP INTERFACE ARCHITECTURE
- Publication number 20190303328
- Publication date Oct 3, 2019
- Xilinx, Inc.
- Goran H.K. Balski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING ENGINE TILE ARCHITECTURE FOR AN INTEGRATED CIRCUIT
- Publication number 20190303347
- Publication date Oct 3, 2019
- Xilinx, Inc.
- Goran H.K. Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
- Publication number 20190303033
- Publication date Oct 3, 2019
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE WITH DATA PROCESSING ENGINE ARRAY
- Publication number 20190303311
- Publication date Oct 3, 2019
- Xilinx, Inc.
- Goran HK Bilski
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Device with data processing engine array that enables partial recon...

Data processing engine arrangement in a device

Communicating between data processing engines using shared memory

Multi-addressing mode for DMA and non-sequential read and write pat...

Device with data processing engine array that enables partial recon...

Data processing engine arrangement in a device

Event-based debug, trace, and profile in device with data processin...

Memory tiles in data processing engine array

Data processing engines with cascade connected cores

Communicating between data processing engines using shared memory

Data processing engine tile architecture for an integrated circuit

Data processing engine array architecture with memory tiles

Multi-port stream switch for stream interconnect network

Data processing engine array architecture with memory tiles

Dual mode interconnect

Data selection network for a data processing engine in an integrate...

Cascade streaming between data processing engines in an array

Streaming interconnect architecture for data processing engine array

Data processing engine arrangement in a device

Device with data processing engine array that enables partial recon...

Device with data processing engine array

Core for a data processing engine in an integrated circuit

System-on-chip interface architecture

Stall logic for a data processing engine in an integrated circuit

Patents Applicationslast 30 patents

DEVICE WITH DATA PROCESSING ENGINE ARRAY THAT ENABLES PARTIAL RECON...

DEVICE WITH DATA PROCESSING ENGINE ARRAY THAT ENABLES PARTIAL RECON...

DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE

COMMUNICATING BETWEEN DATA PROCESSING ENGINES USING SHARED MEMORY

DATA PROCESSING ENGINE TILE ARCHITECTURE FOR AN INTEGRATED CIRCUIT

DUAL MODE INTERCONNECT

SYSTEM-ON-CHIP INTERFACE ARCHITECTURE

DATA PROCESSING ENGINE TILE ARCHITECTURE FOR AN INTEGRATED CIRCUIT

DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE

DEVICE WITH DATA PROCESSING ENGINE ARRAY