Janakiraman Viraraghavan

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Generic design rule checking (DRC) test case extraction
- Patent number 9,990,458
- Issue date Jun 5, 2018
- International Business Machines Corporation
- Davinder Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test method and structure for integrated circuits before complete m...
- Patent number 9,859,177
- Issue date Jan 2, 2018
- GLOBALFOUNDRIES Inc.
- Janakiraman Viraraghavan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-bit 3-T high density MTPROM array
- Patent number 9,786,333
- Issue date Oct 10, 2017
- GLOBALFOUNDRIES Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Distributed current source/sink using inactive memory elements
- Patent number 9,721,673
- Issue date Aug 1, 2017
- GLOBALFOUNDRIES Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Post-layout thermal-aware integrated circuit performance modeling
- Patent number 9,721,059
- Issue date Aug 1, 2017
- GLOBALFOUNDRIES Inc.
- Tamilmani Ethirajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-bit 3-T high density MTPROM array
- Patent number 9,659,604
- Issue date May 23, 2017
- GLOBALFOUNDRIES Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Disturb free bitcell and array
- Patent number 9,589,658
- Issue date Mar 7, 2017
- GLOBALFOUNDRIES INC.
- Navin Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Generic design rule checking (DRC) test case extraction
- Patent number 9,292,652
- Issue date Mar 22, 2016
- International Business Machines Corporation
- Davinder Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated design rule checking (DRC) test case generation
- Patent number 8,875,064
- Issue date Oct 28, 2014
- International Business Machines Corporation
- Davinder Aggarwal
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TEST METHOD AND STRUCTURE FOR INTEGRATED CIRCUITS BEFORE COMPLETE M...
- Publication number 20170256468
- Publication date Sep 7, 2017
- GLOBALFOUNDRIES INC.
- Janakiraman Viraraghavan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POST-LAYOUT THERMAL-AWARE INTEGRATED CIRCUIT PERFORMANCE MODELING
- Publication number 20170212978
- Publication date Jul 27, 2017
- GLOBALFOUNDRIES INC.
- Tamilmani Ethirajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
- Publication number 20170206938
- Publication date Jul 20, 2017
- GLOBALFOUNDRIES INC.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
- Publication number 20170162234
- Publication date Jun 8, 2017
- GLOBALFOUNDRIES INC.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Application
DISTURB FREE BITCELL AND ARRAY
- Publication number 20170053705
- Publication date Feb 23, 2017
- GLOBALFOUNDRIES Inc.
- Navin AGARWAL
- G11 - INFORMATION STORAGE
Information Patent Application
GENERIC DESIGN RULE CHECKING (DRC) TEST CASE EXTRACTION
- Publication number 20160162628
- Publication date Jun 9, 2016
- International Business Machines Corporation
- Davinder AGGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERIC DESIGN RULE CHECKING (DRC) TEST CASE EXTRACTION
- Publication number 20150324510
- Publication date Nov 12, 2015
- International Business Machines Corporation
- Davinder AGGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATED DESIGN RULE CHECKING (DRC) TEST CASE GENERATION
- Publication number 20140282329
- Publication date Sep 18, 2014
- International Business Machines Corporation
- Davinder AGGARWAL
- G06 - COMPUTING CALCULATING COUNTING

Janakiraman Viraraghavan

Person

Patents Grantslast 30 patents

Generic design rule checking (DRC) test case extraction

Test method and structure for integrated circuits before complete m...

Dual-bit 3-T high density MTPROM array

Distributed current source/sink using inactive memory elements

Post-layout thermal-aware integrated circuit performance modeling

Dual-bit 3-T high density MTPROM array

Disturb free bitcell and array

Generic design rule checking (DRC) test case extraction

Automated design rule checking (DRC) test case generation

Patents Applicationslast 30 patents

TEST METHOD AND STRUCTURE FOR INTEGRATED CIRCUITS BEFORE COMPLETE M...

POST-LAYOUT THERMAL-AWARE INTEGRATED CIRCUIT PERFORMANCE MODELING

DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY

DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY

DISTURB FREE BITCELL AND ARRAY

GENERIC DESIGN RULE CHECKING (DRC) TEST CASE EXTRACTION

GENERIC DESIGN RULE CHECKING (DRC) TEST CASE EXTRACTION

AUTOMATED DESIGN RULE CHECKING (DRC) TEST CASE GENERATION