Janet L. Olson

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Design-for-testability (DFT) insertion at register-transfer-level (...
- Patent number 10,372,858
- Issue date Aug 6, 2019
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing an integrated circuit (IC) design comprising at least on...
- Patent number 10,354,032
- Issue date Jul 16, 2019
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying and using slices in an integrated circuit (IC) design
- Patent number 9,697,314
- Issue date Jul 4, 2017
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Creating and using a wide-bus data structure to represent a wide-bu...
- Patent number 9,690,890
- Issue date Jun 27, 2017
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Creating and using a wide-gate data structure to represent a wide-g...
- Patent number 9,652,573
- Issue date May 16, 2017
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Path dependent power modeling
- Patent number 6,480,815
- Issue date Nov 12, 2002
- Synopsys, Inc.
- Janet Olson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional power modeling table having dual output capacitan...
- Patent number 6,195,630
- Issue date Feb 27, 2001
- Synopsys, Inc.
- Ashutosh S. Mauskar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Path dependent power modeling
- Patent number 5,949,689
- Issue date Sep 7, 1999
- Synopsys, Inc.
- Janet Olson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional power modeling table having dual output capacitan...
- Patent number 5,903,476
- Issue date May 11, 1999
- Synopsys, Inc.
- Ashutosh S. Mauskar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State dependent power modeling
- Patent number 5,838,579
- Issue date Nov 17, 1998
- Synopsys, Inc.
- Janet Olson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DESIGN-FOR-TESTABILITY (DFT) INSERTION AT REGISTER-TRANSFER-LEVEL (...
- Publication number 20180246996
- Publication date Aug 30, 2018
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING AN INTEGRATED CIRCUIT (IC) DESIGN COMPRISING AT LEAST ON...
- Publication number 20180107777
- Publication date Apr 19, 2018
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING

Janet L. Olson

Person

Patents Grantslast 30 patents

Design-for-testability (DFT) insertion at register-transfer-level (...

Optimizing an integrated circuit (IC) design comprising at least on...

Identifying and using slices in an integrated circuit (IC) design

Creating and using a wide-bus data structure to represent a wide-bu...

Creating and using a wide-gate data structure to represent a wide-g...

Path dependent power modeling

Three-dimensional power modeling table having dual output capacitan...

Path dependent power modeling

Three-dimensional power modeling table having dual output capacitan...

State dependent power modeling

Patents Applicationslast 30 patents

DESIGN-FOR-TESTABILITY (DFT) INSERTION AT REGISTER-TRANSFER-LEVEL (...

OPTIMIZING AN INTEGRATED CIRCUIT (IC) DESIGN COMPRISING AT LEAST ON...