Jangseok CHOI

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
DRAM assist error correction mechanism for DDR SDRAM interface
- Patent number 12,242,344
- Issue date Mar 4, 2025
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous communication protocol compatible with synchronous DDR...
- Patent number 12,189,546
- Issue date Jan 7, 2025
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous communication protocol compatible with synchronous DDR...
- Patent number 12,147,360
- Issue date Nov 19, 2024
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordinated in-module RAS features for synchronous DDR compatible m...
- Patent number 12,032,828
- Issue date Jul 9, 2024
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM assist error correction mechanism for DDR SDRAM interface
- Patent number 11,625,296
- Issue date Apr 11, 2023
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous communication protocol compatible with synchronous DDR...
- Patent number 11,397,698
- Issue date Jul 26, 2022
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordinated in-module RAS features for synchronous DDR compatible m...
- Patent number 11,294,571
- Issue date Apr 5, 2022
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM assist error correction mechanism for DDR SDRAM interface
- Patent number 11,010,242
- Issue date May 18, 2021
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM assist error correction mechanism for DDR SDRAM interface
- Patent number 10,977,118
- Issue date Apr 13, 2021
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous communication protocol compatible with synchronous DDR...
- Patent number 10,621,119
- Issue date Apr 14, 2020
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordinated in-module RAS features for synchronous DDR compatible m...
- Patent number 10,592,114
- Issue date Mar 17, 2020
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for addressing high capacity SDRAM-like memory without incr...
- Patent number 10,504,572
- Issue date Dec 10, 2019
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM assist error correction mechanism for DDR SDRAM interface
- Patent number 10,268,541
- Issue date Apr 23, 2019
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for addressing high capacity SDRAM-like memory without incr...
- Patent number 9,837,135
- Issue date Dec 5, 2017
- Samsung Electronics Co., Ltd.
- Mu-Tien Chang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...
- Publication number 20250036584
- Publication date Jan 30, 2025
- Samsung Electronics Co., Ltd.
- Dimin NIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...
- Publication number 20240143173
- Publication date May 2, 2024
- Samsung Electronics Co., Ltd.
- Mu-Tien CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
- Publication number 20230229555
- Publication date Jul 20, 2023
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...
- Publication number 20220358060
- Publication date Nov 10, 2022
- Samsung Electronics Co., Ltd.
- Dimin NIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...
- Publication number 20220229551
- Publication date Jul 21, 2022
- Samsung Electronics Co., Ltd.
- Mu-Tien CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
- Publication number 20210294697
- Publication date Sep 23, 2021
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...
- Publication number 20200218447
- Publication date Jul 9, 2020
- Samsung Electronics Co., Ltd.
- Mu-Tien CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...
- Publication number 20200167297
- Publication date May 28, 2020
- Samsung Electronics Co., Ltd.
- Dimin NIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
- Publication number 20190179704
- Publication date Jun 13, 2019
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
- Publication number 20190179705
- Publication date Jun 13, 2019
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR ADDRESSING HIGH CAPACITY SDRAM-LIKE MEMORY WITHOUT INCR...
- Publication number 20180102152
- Publication date Apr 12, 2018
- SAMSUNG ELECTRONICS CO., LTD.
- Mu-Tien CHANG
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
- Publication number 20180046541
- Publication date Feb 15, 2018
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...
- Publication number 20170255575
- Publication date Sep 7, 2017
- Samsung Electronics Co., Ltd.
- Dimin NIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...
- Publication number 20170255383
- Publication date Sep 7, 2017
- Samsung Electronics Co., Ltd.
- Mu-Tien CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR ADDRESSING HIGH CAPACITY SDRAM-LIKE MEMORY WITHOUT INCR...
- Publication number 20170256311
- Publication date Sep 7, 2017
- Samsung Electronics Co., Ltd.
- Mu-Tien CHANG
- G11 - INFORMATION STORAGE

Jangseok CHOI

Person

Patents Grantslast 30 patents

DRAM assist error correction mechanism for DDR SDRAM interface

Asynchronous communication protocol compatible with synchronous DDR...

Asynchronous communication protocol compatible with synchronous DDR...

Coordinated in-module RAS features for synchronous DDR compatible m...

DRAM assist error correction mechanism for DDR SDRAM interface

Asynchronous communication protocol compatible with synchronous DDR...

Coordinated in-module RAS features for synchronous DDR compatible m...

DRAM assist error correction mechanism for DDR SDRAM interface

DRAM assist error correction mechanism for DDR SDRAM interface

Asynchronous communication protocol compatible with synchronous DDR...

Coordinated in-module RAS features for synchronous DDR compatible m...

Methods for addressing high capacity SDRAM-like memory without incr...

DRAM assist error correction mechanism for DDR SDRAM interface

Methods for addressing high capacity SDRAM-like memory without incr...

Patents Applicationslast 30 patents

ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...

COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...

DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE

ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...

COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...

DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE

COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...

ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...

DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE

DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE

METHODS FOR ADDRESSING HIGH CAPACITY SDRAM-LIKE MEMORY WITHOUT INCR...

DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE

ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR...

COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE M...

METHODS FOR ADDRESSING HIGH CAPACITY SDRAM-LIKE MEMORY WITHOUT INCR...