Janusz Rajski

Person

West Linn, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Universal compactor architecture for testing circuits
- Patent number 11,815,555
- Issue date Nov 14, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Grant
Trajectory-optimized test pattern generation for built-in self-test
- Patent number 11,585,853
- Issue date Feb 21, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic stellar built-in self test
- Patent number 11,555,854
- Issue date Jan 17, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Grant
Isometric control data generation for test compression
- Patent number 11,422,188
- Issue date Aug 23, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Yu Huang
- G01 - MEASURING TESTING
Information Patent Grant
Layout-friendly test pattern decompressor
- Patent number 11,232,246
- Issue date Jan 25, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Yu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible isometric decompressor architecture for test compression
- Patent number 11,150,299
- Issue date Oct 19, 2021
- SIEMENS INDUSTRY SOFTWARE INC.
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Prediction of test pattern counts for scan configuration determination
- Patent number 11,010,523
- Issue date May 18, 2021
- SIEMENS INDUSTRY SOFTWARE INC.
- Yu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test generation using testability-based guidance
- Patent number 10,996,273
- Issue date May 4, 2021
- SIEMENS INDUSTRY SOFTWARE INC.
- Sylwester Milewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan cell architecture for improving test coverage and reducing tes...
- Patent number 10,963,612
- Issue date Mar 30, 2021
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test scheduling and test access in test compression environment
- Patent number 10,955,460
- Issue date Mar 23, 2021
- Mentor Graphics Corporation
- Mark Kassab
- G01 - MEASURING TESTING
Information Patent Grant
Signal probability-based test cube reordering and merging
- Patent number 10,830,815
- Issue date Nov 10, 2020
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Efficient and flexible network for streaming data in circuits
- Patent number 10,788,530
- Issue date Sep 29, 2020
- Mentor Graphics Corporation
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Grant
Streaming networks efficiency using data throttling
- Patent number 10,775,436
- Issue date Sep 15, 2020
- Mentor Graphics Corporation
- Jean-Francois Cote
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test application time reduction using capture-per-cycle test points
- Patent number 10,509,072
- Issue date Dec 17, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Timing-aware test generation and fault simulation
- Patent number 10,509,073
- Issue date Dec 17, 2019
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data streaming for testing identical circuit blocks
- Patent number 10,473,721
- Issue date Nov 12, 2019
- Mentor Graphics Corporation
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Grant
Data generation for streaming networks in circuits
- Patent number 10,476,740
- Issue date Nov 12, 2019
- Mentor Graphics Corporation
- Jean-Francois Cote
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Test point insertion for low test pattern counts
- Patent number 10,444,282
- Issue date Oct 15, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain stitching for test-per-clock
- Patent number 10,379,161
- Issue date Aug 13, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test point-enhanced hardware security
- Patent number 10,361,873
- Issue date Jul 23, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Continuous application and decompression of test patterns and selec...
- Patent number 10,234,506
- Issue date Mar 19, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Transition test generation for detecting cell internal defects
- Patent number 10,222,420
- Issue date Mar 5, 2019
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power testing based on dynamic grouping of scan
- Patent number 10,120,029
- Issue date Nov 6, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Multi-stage test response compactors
- Patent number 10,120,024
- Issue date Nov 6, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic built-in self-test based on compressed test patterns...
- Patent number 9,933,485
- Issue date Apr 3, 2018
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Channel sharing for testing circuits having non-identical cores
- Patent number 9,915,702
- Issue date Mar 13, 2018
- Mentor Graphics Corporation
- Yu Huang
- G01 - MEASURING TESTING
Information Patent Grant
Selective per-cycle masking of scan chains for system level test
- Patent number 9,874,606
- Issue date Jan 23, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-stage test response compactors
- Patent number 9,778,316
- Issue date Oct 3, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Timing-aware test generation and fault simulation
- Patent number 9,720,040
- Issue date Aug 1, 2017
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan-based test architecture for interconnects in stacked designs
- Patent number 9,720,041
- Issue date Aug 1, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
X-Masking for In-System Deterministic Test
- Publication number 20240337693
- Publication date Oct 10, 2024
- Siemens Industry Software Inc.
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test Generation for Structurally Similar Circuits
- Publication number 20240160823
- Publication date May 16, 2024
- Siemens Industry Software Inc.
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIVERSAL COMPACTOR ARCHITECTURE FOR TESTING CIRCUITS
- Publication number 20220308110
- Publication date Sep 29, 2022
- Siemens Industry Software Inc.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Application
DETERMINISTIC STELLAR BUILT-IN SELF TEST
- Publication number 20210373077
- Publication date Dec 2, 2021
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Application
Trajectory-Optimized Test Pattern Generation for Built-In Self-Test
- Publication number 20210156918
- Publication date May 27, 2021
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
Layout-Friendly Test Pattern Decompressor
- Publication number 20210150112
- Publication date May 20, 2021
- Mentor Graphics Corporation
- Yu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE ISOMETRIC DECOMPRESSOR ARCHITECTURE FOR TEST COMPRESSION
- Publication number 20210018563
- Publication date Jan 21, 2021
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Scan Cell Architecture For Improving Test Coverage And Reducing Tes...
- Publication number 20200327268
- Publication date Oct 15, 2020
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deep Learning Based Test Compression Analyzer
- Publication number 20190311290
- Publication date Oct 10, 2019
- Mentor Graphics Corporation
- Yu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test Generation Using Testability-Based Guidance
- Publication number 20190293718
- Publication date Sep 26, 2019
- Mentor Graphics Corporation
- Sylwester Milewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Signal Probability-Based Test Cube Reordering And Merging
- Publication number 20190293713
- Publication date Sep 26, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Isometric Control Data Generation For Test Compression
- Publication number 20190293717
- Publication date Sep 26, 2019
- Mentor Graphics Corporation
- Yu Huang
- G01 - MEASURING TESTING
Information Patent Application
Test Application Time Reduction Using Capture-Per-Cycle Test Points
- Publication number 20180252768
- Publication date Sep 6, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
MULTI-STAGE TEST RESPONSE COMPACTORS
- Publication number 20180156867
- Publication date Jun 7, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20180143249
- Publication date May 24, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
TIMING-AWARE TEST GENERATION AND FAULT SIMULATION
- Publication number 20180045780
- Publication date Feb 15, 2018
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...
- Publication number 20180017622
- Publication date Jan 18, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
TRANSITION TEST GENERATION FOR DETECTING CELL INTERNAL DEFECTS
- Publication number 20170193155
- Publication date Jul 6, 2017
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test Point-Enhanced Hardware Security
- Publication number 20170141930
- Publication date May 18, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20170052227
- Publication date Feb 23, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
MULTI-STAGE TEST RESPONSE COMPACTORS
- Publication number 20160320450
- Publication date Nov 3, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN...
- Publication number 20160252573
- Publication date Sep 1, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Deterministic Built-In Self-Test
- Publication number 20160245863
- Publication date Aug 25, 2016
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
Test Point Insertion For Low Test Pattern Counts
- Publication number 20160109517
- Publication date Apr 21, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Low Power Testing Based On Dynamic Grouping Of Scan
- Publication number 20150323597
- Publication date Nov 12, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
TIMING-AWARE TEST GENERATION AND FAULT SIMULATION
- Publication number 20150323600
- Publication date Nov 12, 2015
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
Test Scheduling and Test Access in Test Compression Environment
- Publication number 20150285854
- Publication date Oct 8, 2015
- Mark A. Kassab
- G01 - MEASURING TESTING
Information Patent Application
Isometric Test Compression With Low Toggling Activity
- Publication number 20150253385
- Publication date Sep 10, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES
- Publication number 20150160290
- Publication date Jun 11, 2015
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Application
Dynamic Shift For Test Pattern Compression
- Publication number 20150153410
- Publication date Jun 4, 2015
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING

Janusz Rajski

Person

Patents Grantslast 30 patents

Universal compactor architecture for testing circuits

Trajectory-optimized test pattern generation for built-in self-test

Deterministic stellar built-in self test

Isometric control data generation for test compression

Layout-friendly test pattern decompressor

Flexible isometric decompressor architecture for test compression

Prediction of test pattern counts for scan configuration determination

Test generation using testability-based guidance

Scan cell architecture for improving test coverage and reducing tes...

Test scheduling and test access in test compression environment

Signal probability-based test cube reordering and merging

Efficient and flexible network for streaming data in circuits

Streaming networks efficiency using data throttling

Test application time reduction using capture-per-cycle test points

Timing-aware test generation and fault simulation

Data streaming for testing identical circuit blocks

Data generation for streaming networks in circuits

Test point insertion for low test pattern counts

Scan chain stitching for test-per-clock

Test point-enhanced hardware security

Continuous application and decompression of test patterns and selec...

Transition test generation for detecting cell internal defects

Low power testing based on dynamic grouping of scan

Multi-stage test response compactors

Deterministic built-in self-test based on compressed test patterns...

Channel sharing for testing circuits having non-identical cores

Selective per-cycle masking of scan chains for system level test

Multi-stage test response compactors

Timing-aware test generation and fault simulation

Scan-based test architecture for interconnects in stacked designs

Patents Applicationslast 30 patents

X-Masking for In-System Deterministic Test

Test Generation for Structurally Similar Circuits

UNIVERSAL COMPACTOR ARCHITECTURE FOR TESTING CIRCUITS

DETERMINISTIC STELLAR BUILT-IN SELF TEST

Trajectory-Optimized Test Pattern Generation for Built-In Self-Test

Layout-Friendly Test Pattern Decompressor

FLEXIBLE ISOMETRIC DECOMPRESSOR ARCHITECTURE FOR TEST COMPRESSION

Scan Cell Architecture For Improving Test Coverage And Reducing Tes...

Deep Learning Based Test Compression Analyzer

Test Generation Using Testability-Based Guidance

Signal Probability-Based Test Cube Reordering And Merging

Isometric Control Data Generation For Test Compression

Test Application Time Reduction Using Capture-Per-Cycle Test Points

MULTI-STAGE TEST RESPONSE COMPACTORS

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...

TRANSITION TEST GENERATION FOR DETECTING CELL INTERNAL DEFECTS

Test Point-Enhanced Hardware Security

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

MULTI-STAGE TEST RESPONSE COMPACTORS

TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN...

Deterministic Built-In Self-Test

Test Point Insertion For Low Test Pattern Counts

Low Power Testing Based On Dynamic Grouping Of Scan

TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

Test Scheduling and Test Access in Test Compression Environment

Isometric Test Compression With Low Toggling Activity

ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES

Dynamic Shift For Test Pattern Compression