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Jaroslaw A. Magera
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Palatine, IL, US
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Patents Grants
last 30 patents
Information
Patent Grant
Printed circuit board having closed vias
Patent number
7,557,304
Issue date
Jul 7, 2009
Motorola, Inc.
Jaroslaw A. Magera
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Grant
Printed circuit board
Patent number
7,459,202
Issue date
Dec 2, 2008
Motorola, Inc.
Jaroslaw A. Magera
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Grant
Method for fabricating a printed circuit board
Patent number
7,451,540
Issue date
Nov 18, 2008
Motorola, Inc.
Jaroslaw A. Magera
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Grant
Method for fabricating closed vias in a printed circuit board
Patent number
7,427,562
Issue date
Sep 23, 2008
Motorla, Inc.
Jaroslaw A. Magera
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Grant
Capacitance laminate and printed circuit board apparatus and method
Patent number
7,361,847
Issue date
Apr 22, 2008
Motorola, Inc.
Gregory J. Dunn
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Grant
Printed circuit patterned embedded capacitance layer
Patent number
7,138,068
Issue date
Nov 21, 2006
Motorola, Inc.
Gregory J. Dunn
C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Patents Applications
last 30 patents
Information
Patent Application
METHOD OF FILLING VIAS WITH FUSIBLE METAL
Publication number
20090218124
Publication date
Sep 3, 2009
MOTOROLA, INC.
JAROSLAW A. MAGERA
Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information
Patent Application
METHODS FOR MAKING PRINTED WIRING BOARDS
Publication number
20080148561
Publication date
Jun 26, 2008
MOTOROLA, INC.
Jaroslaw A. Magera
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Application
PRINTED CIRCUIT BOARD HAVING CLOSED VIAS
Publication number
20080121420
Publication date
May 29, 2008
MOTOROLA, INC.
Jaroslaw A. Magera
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Application
METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD
Publication number
20080119041
Publication date
May 22, 2008
MOTOROLA, INC.
Jaroslaw A. Magera
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Application
METHOD FOR FABRICATING A PRINTED CIRCUIT BOARD
Publication number
20080092376
Publication date
Apr 24, 2008
MOTOROLA, INC.
Jaroslaw A. Magera
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Application
PRINTED CIRCUIT BOARD
Publication number
20080003414
Publication date
Jan 3, 2008
MOTOROLA, INC.
Jaroslaw A. Magera
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Application
Capacitance laminate and printed circuit board apparatus and method
Publication number
20070151758
Publication date
Jul 5, 2007
Gregory J. Dunn
H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information
Patent Application
Printed circuit patterned embedded capacitance layer
Publication number
20060207970
Publication date
Sep 21, 2006
Gregory J. Dunn
C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...