Jason H. Anderson

Person

Toronto, CA

People

Patents Grantslast 30 patents

Information Patent Grant
High-level synthesis (HLS) method and apparatus to specify parallel...
- Patent number 11,816,406
- Issue date Nov 14, 2023
- Microchip Technology Inc.
- Jongsok Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level synthesis (HLS) method and apparatus to specify pipeline...
- Patent number 11,055,456
- Issue date Jul 6, 2021
- Microchip Technology Inc.
- Jongsok Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level synthesis (HLS) method and apparatus to specify pipeline...
- Patent number 10,579,762
- Issue date Mar 3, 2020
- LegUp Computing Inc.
- Jongsok Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit
- Patent number 9,742,405
- Issue date Aug 22, 2017
- Fujitsu Limited
- Hirotaka Tamura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for designing semiconductor integrated circuit and program
- Patent number 9,213,796
- Issue date Dec 15, 2015
- Fujitsu Limited
- Hirotaka Tamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread synchronization by transitioning threads to spin lock and sl...
- Patent number 9,003,413
- Issue date Apr 7, 2015
- Xilinx, Inc.
- Jason H. Anderson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-threaded deterministic router
- Patent number 8,671,379
- Issue date Mar 11, 2014
- Xilinx, Inc.
- Jitu Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threaded deterministic router
- Patent number 8,312,409
- Issue date Nov 13, 2012
- Xilinx, Inc.
- Gitu Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of and system for generating a logic configuration for an in...
- Patent number 8,205,180
- Issue date Jun 19, 2012
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing clock signal power consumption wi...
- Patent number 8,201,127
- Issue date Jun 12, 2012
- Xilinx, Inc.
- Qiang Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Patterns for routing nets in a programmable logic device
- Patent number 7,797,665
- Issue date Sep 14, 2010
- Xilinx, Inc.
- Hui Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for technology mapping considering boolean flexibility
- Patent number 7,735,047
- Issue date Jun 8, 2010
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for facilitating signal routing within a progr...
- Patent number 7,725,868
- Issue date May 25, 2010
- Xilinx, Inc.
- Vinay Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of reducing power of a circuit
- Patent number 7,653,891
- Issue date Jan 26, 2010
- Xilinx, Inc.
- Jason H. Anderson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for power optimization using don't care condit...
- Patent number 7,603,646
- Issue date Oct 13, 2009
- Xilinx, Inc.
- Tetse Jang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing constraints in computer-aided design for integrated circ...
- Patent number 7,555,734
- Issue date Jun 30, 2009
- Xilinx, Inc.
- Qiang Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified placer infrastructure
- Patent number 7,398,496
- Issue date Jul 8, 2008
- Xilinx, Inc.
- James L. Saunders
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for facilitating signal routing within a progr...
- Patent number 7,306,977
- Issue date Dec 11, 2007
- Xilinx, Inc.
- Vinay Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for application of network flow techniques under constraints
- Patent number 7,143,380
- Issue date Nov 28, 2006
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental routing in integrated circuit design
- Patent number 7,134,112
- Issue date Nov 7, 2006
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-layout optimization in integrated circuit design
- Patent number 7,111,268
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for computing and using future costing data in signal routing
- Patent number 7,073,155
- Issue date Jul 4, 2006
- Xilinx, Inc.
- Raymond Kong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leakage power optimization for integrated circuits
- Patent number 6,993,737
- Issue date Jan 31, 2006
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified placer infrastructure
- Patent number 6,983,439
- Issue date Jan 3, 2006
- Xilinx, Inc.
- James L. Saunders
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental placement of design objects in integrated circuit design
- Patent number 6,871,336
- Issue date Mar 22, 2005
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of objects with partial shape restriction
- Patent number 6,857,115
- Issue date Feb 15, 2005
- Xilinx, Inc.
- Srinivasan Dasasathyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for computing and using future costing data in signal routing
- Patent number 6,851,101
- Issue date Feb 1, 2005
- Xilinx, Inc.
- Raymond Kong
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIGH-LEVEL SYNTHESIS (HLS) METHOD AND APPARATUS TO SPECIFY PARALLEL...
- Publication number 20210294948
- Publication date Sep 23, 2021
- LegUp Computing Inc.
- Jongsok Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-LEVEL SYNTHESIS (HLS) METHOD AND APPARATUS TO SPECIFY PIPELINE...
- Publication number 20200117844
- Publication date Apr 16, 2020
- LegUp Computing Inc.
- Jongsok Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-LEVEL SYNTHESIS (HLS) METHOD AND APPARATUS TO SPECIFY PIPELINE...
- Publication number 20180330022
- Publication date Nov 15, 2018
- LegUp Computing Inc.
- Jongsok Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT
- Publication number 20150061410
- Publication date Mar 5, 2015
- Fujitsu Limited
- Hirotaka TAMURA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM
- Publication number 20150067630
- Publication date Mar 5, 2015
- Fujitsu Limited
- Hirotaka TAMURA
- G06 - COMPUTING CALCULATING COUNTING

Jason H. Anderson

Person

Patents Grantslast 30 patents

High-level synthesis (HLS) method and apparatus to specify parallel...

High-level synthesis (HLS) method and apparatus to specify pipeline...

High-level synthesis (HLS) method and apparatus to specify pipeline...

Semiconductor integrated circuit

Method for designing semiconductor integrated circuit and program

Thread synchronization by transitioning threads to spin lock and sl...

Multi-threaded deterministic router

Multi-threaded deterministic router

Method of and system for generating a logic configuration for an in...

Method and apparatus for reducing clock signal power consumption wi...

Patterns for routing nets in a programmable logic device

Method for technology mapping considering boolean flexibility

Method and apparatus for facilitating signal routing within a progr...

Method of reducing power of a circuit

Method and apparatus for power optimization using don't care condit...

Processing constraints in computer-aided design for integrated circ...

Unified placer infrastructure

Method and apparatus for facilitating signal routing within a progr...

Method for application of network flow techniques under constraints

Incremental routing in integrated circuit design

Post-layout optimization in integrated circuit design

Method for computing and using future costing data in signal routing

Leakage power optimization for integrated circuits

Unified placer infrastructure

Incremental placement of design objects in integrated circuit design

Placement of objects with partial shape restriction

Method for computing and using future costing data in signal routing

Patents Applicationslast 30 patents

HIGH-LEVEL SYNTHESIS (HLS) METHOD AND APPARATUS TO SPECIFY PARALLEL...

HIGH-LEVEL SYNTHESIS (HLS) METHOD AND APPARATUS TO SPECIFY PIPELINE...

HIGH-LEVEL SYNTHESIS (HLS) METHOD AND APPARATUS TO SPECIFY PIPELINE...

SEMICONDUCTOR INTEGRATED CIRCUIT

METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM