JASON L. FRANKEL

Person

Hopewell Junction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Phase aligning and calibrating clocks from one phase lock loop (PLL...
- Patent number 12,111,684
- Issue date Oct 8, 2024
- International Business Machines Corporation
- Douglas J. Malone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase aligning and calibrating clocks from one phase lock loop (PLL...
- Patent number 11,775,004
- Issue date Oct 3, 2023
- International Business Machines Corporation
- Douglas J. Malone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor package floating metal checks
- Patent number 10,949,600
- Issue date Mar 16, 2021
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated generation of surface-mount package design
- Patent number 10,706,204
- Issue date Jul 7, 2020
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor package floating metal checks
- Patent number 10,423,751
- Issue date Sep 24, 2019
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Crosstalk reduction between signal layers in a multilayered package...
- Patent number 10,375,820
- Issue date Aug 6, 2019
- International Business Machines Corporation
- Jinwoo Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Crosstalk reduction between signal layers in a multilayered package...
- Patent number 9,955,567
- Issue date Apr 24, 2018
- International Business Machines Corporation
- Jinwoo Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Crosstalk reduction between signal layers in a multilayered package...
- Patent number 8,927,879
- Issue date Jan 6, 2015
- International Business Machines Corporation
- Jinwoo Choi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Structure for implementing secure multichip modules for encryption...
- Patent number 7,806,341
- Issue date Oct 5, 2010
- International Business Machines Corporation
- Mukta G. Farooq
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and structure for implementing secure multichip modules for...
- Patent number 7,472,836
- Issue date Jan 6, 2009
- International Business Machines Corporation
- Mukta G. Farooq
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for noise reduction in multi-layer ceramic packages
- Patent number 7,348,667
- Issue date Mar 25, 2008
- International Business Machines Corporation
- Sungjun Chun
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Nested design approach
- Patent number 7,325,213
- Issue date Jan 29, 2008
- International Business Machines Corporation
- Harsaran S. Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for implementing secure multichip modules for...
- Patent number 7,281,667
- Issue date Oct 16, 2007
- International Business Machines Corporation
- Mukta G. Farooq
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mesh plane generation and file storage
- Patent number 7,096,451
- Issue date Aug 22, 2006
- International Business Machines Corporation
- Alice L. Donaldson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Jogging structure for wiring translation between grids with non-int...
- Patent number 6,974,722
- Issue date Dec 13, 2005
- International Business Machines Corporation
- Glenn G. Daves
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Jogging structure for wiring translation between grids with non-int...
- Patent number 6,762,489
- Issue date Jul 13, 2004
- International Business Machines Corporation
- Glenn G. Daves
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Universal cost reduced substrate structure method and apparatus
- Patent number 5,946,552
- Issue date Aug 31, 1999
- International Business Machines Corporation
- Kenneth Alfred Bird
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic component package with decoupling capacitors completely...
- Patent number 5,831,810
- Issue date Nov 3, 1998
- International Business Machines Corporation
- Kenneth A. Bird
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PHASE ALIGNING AND CALIBRATING CLOCKS FROM ONE PHASE LOCK LOOP (PLL...
- Publication number 20230393610
- Publication date Dec 7, 2023
- International Business Machines Corporation
- Douglas J. Malone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALIGNING AND CALIBRATING CLOCKS FROM ONE PHASE LOCK LOOP (PLL...
- Publication number 20230085155
- Publication date Mar 16, 2023
- International Business Machines Corporation
- Douglas J. Malone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATED GENERATION OF SURFACE-MOUNT PACKAGE DESIGN
- Publication number 20200104454
- Publication date Apr 2, 2020
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS
- Publication number 20190362049
- Publication date Nov 28, 2019
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS
- Publication number 20190102505
- Publication date Apr 4, 2019
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...
- Publication number 20180213636
- Publication date Jul 26, 2018
- JINWOO CHOI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...
- Publication number 20140331482
- Publication date Nov 13, 2014
- JINWOO CHOI
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...
- Publication number 20120125677
- Publication date May 24, 2012
- International Business Machines Corporation
- Jinwoo Choi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
STRUCTURE FOR IMPLEMENTING SECURE MULTICHIP MODULES FOR ENCRYPTION...
- Publication number 20090145973
- Publication date Jun 11, 2009
- International Business Machines Corporation
- Mukta G. Farooq
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND STRUCTURE FOR IMPLEMENTING SECURE MULTICHIP MODULES FOR...
- Publication number 20080000988
- Publication date Jan 3, 2008
- International Business Machines Corporation
- Mukta G. Farooq
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Noise Reduction in Multi-Layer Ceramic Packages
- Publication number 20070080436
- Publication date Apr 12, 2007
- IBM CORPORATION
- Sungjun Chun
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD AND STRUCTURE FOR IMPLEMENTING SECURE MULTICHIP MODULES FOR...
- Publication number 20060231633
- Publication date Oct 19, 2006
- International Business Machines Corporation
- Mukta G. Farooq
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for noise reduction in multi-layer ceramic packages
- Publication number 20060214190
- Publication date Sep 28, 2006
- Sungjun Chun
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
NESTED DESIGN APPROACH
- Publication number 20050278674
- Publication date Dec 15, 2005
- International Business Machines Corporation
- Harsaran S. Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MESH PLANE GENERATION AND FILE STORAGE
- Publication number 20050055660
- Publication date Mar 10, 2005
- Alice L. Donaldson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JOGGING STRUCTURE FOR WIRING TRANSLATION BETWEEN GRIDS WITH NON-INT...
- Publication number 20040188823
- Publication date Sep 30, 2004
- International Business Machines Corporation
- Glenn G. Daves
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Structure and method for wiring translation between grids with non-...
- Publication number 20030094687
- Publication date May 22, 2003
- Glenn G. Daves
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

JASON L. FRANKEL

Person

Patents Grantslast 30 patents

Phase aligning and calibrating clocks from one phase lock loop (PLL...

Phase aligning and calibrating clocks from one phase lock loop (PLL...

Semiconductor package floating metal checks

Automated generation of surface-mount package design

Semiconductor package floating metal checks

Crosstalk reduction between signal layers in a multilayered package...

Crosstalk reduction between signal layers in a multilayered package...

Crosstalk reduction between signal layers in a multilayered package...

Structure for implementing secure multichip modules for encryption...

Method and structure for implementing secure multichip modules for...

System and method for noise reduction in multi-layer ceramic packages

Nested design approach

Method and structure for implementing secure multichip modules for...

Mesh plane generation and file storage

Jogging structure for wiring translation between grids with non-int...

Jogging structure for wiring translation between grids with non-int...

Universal cost reduced substrate structure method and apparatus

Electronic component package with decoupling capacitors completely...

Patents Applicationslast 30 patents

PHASE ALIGNING AND CALIBRATING CLOCKS FROM ONE PHASE LOCK LOOP (PLL...

PHASE ALIGNING AND CALIBRATING CLOCKS FROM ONE PHASE LOCK LOOP (PLL...

AUTOMATED GENERATION OF SURFACE-MOUNT PACKAGE DESIGN

SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS

SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS

CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...

CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...

CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...

STRUCTURE FOR IMPLEMENTING SECURE MULTICHIP MODULES FOR ENCRYPTION...

METHOD AND STRUCTURE FOR IMPLEMENTING SECURE MULTICHIP MODULES FOR...

System and Method for Noise Reduction in Multi-Layer Ceramic Packages

METHOD AND STRUCTURE FOR IMPLEMENTING SECURE MULTICHIP MODULES FOR...

System and method for noise reduction in multi-layer ceramic packages

NESTED DESIGN APPROACH

MESH PLANE GENERATION AND FILE STORAGE

JOGGING STRUCTURE FOR WIRING TRANSLATION BETWEEN GRIDS WITH NON-INT...

Structure and method for wiring translation between grids with non-...