Jason L. Nevill

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reducing program verifies for multi-level NAND cells
- Patent number 11,887,680
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid routine for a memory device
- Patent number 11,823,743
- Issue date Nov 21, 2023
- Micron Technology, Inc.
- Shannon Marissa Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device field degradation and factory defect detection by pump clock...
- Patent number 11,482,298
- Issue date Oct 25, 2022
- Micron Technology, Inc.
- Jason Lee Nevill
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing program verifies for multi-level NAND cells
- Patent number 11,417,406
- Issue date Aug 16, 2022
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid routine for a memory device
- Patent number 11,355,200
- Issue date Jun 7, 2022
- Micron Technology, Inc.
- Shannon Marissa Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices configured to perform leak checks
- Patent number 10,665,307
- Issue date May 26, 2020
- Micron Technology, Inc.
- Jeffrey A. Kessenich
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices configured to perform leak checks
- Patent number 10,366,767
- Issue date Jul 30, 2019
- Micron Technology, Inc.
- Jeffrey A. Kessenich
- G01 - MEASURING TESTING
Information Patent Grant
Program operations with embedded leak checks
- Patent number 9,761,322
- Issue date Sep 12, 2017
- Micron Technology, Inc.
- Jeffery A. Kessenich
- G11 - INFORMATION STORAGE
Information Patent Grant
Program operations with embedded leak checks
- Patent number 9,281,078
- Issue date Mar 8, 2016
- Micron Technology, Inc.
- Jeffrey A. Kessenich
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
REDUCING PROGRAM VERIFIES FOR MULTI-LEVEL NAND CELLS
- Publication number 20220359025
- Publication date Nov 10, 2022
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID ROUTINE FOR A MEMORY DEVICE
- Publication number 20220277796
- Publication date Sep 1, 2022
- Micron Technology, Inc.
- Shannon Marissa Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID ROUTINE FOR A MEMORY DEVICE
- Publication number 20220059173
- Publication date Feb 24, 2022
- Micron Technology, Inc.
- Shannon Marissa Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING PROGRAM VERIFIES FOR MULTI-LEVEL NAND CELLS
- Publication number 20210398599
- Publication date Dec 23, 2021
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE FIELD DEGRADATION AND FACTORY DEFECT DETECTION BY PUMP CLOCK...
- Publication number 20210375387
- Publication date Dec 2, 2021
- Micron Technology, Inc.
- Jason Lee Nevill
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES CONFIGURED TO PERFORM LEAK CHECKS
- Publication number 20190287634
- Publication date Sep 19, 2019
- Micron Technology, Inc.
- Jeffrey A. Kessenich
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES CONFIGURED TO PERFORM LEAK CHECKS
- Publication number 20170352431
- Publication date Dec 7, 2017
- Micron Technology, Inc.
- Jeffrey A. Kessenich
- G01 - MEASURING TESTING
Information Patent Application
PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS
- Publication number 20160155513
- Publication date Jun 2, 2016
- Micron Technology, Inc.
- Jeffery A. Kessenich
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS
- Publication number 20150364213
- Publication date Dec 17, 2015
- Micron Technology, Inc.
- Jeffrey A. Kessenich
- G01 - MEASURING TESTING

Jason L. Nevill

Person

Patents Grantslast 30 patents

Reducing program verifies for multi-level NAND cells

Hybrid routine for a memory device

Device field degradation and factory defect detection by pump clock...

Reducing program verifies for multi-level NAND cells

Hybrid routine for a memory device

Memory devices configured to perform leak checks

Memory devices configured to perform leak checks

Program operations with embedded leak checks

Program operations with embedded leak checks

Patents Applicationslast 30 patents

REDUCING PROGRAM VERIFIES FOR MULTI-LEVEL NAND CELLS

HYBRID ROUTINE FOR A MEMORY DEVICE

HYBRID ROUTINE FOR A MEMORY DEVICE

REDUCING PROGRAM VERIFIES FOR MULTI-LEVEL NAND CELLS

DEVICE FIELD DEGRADATION AND FACTORY DEFECT DETECTION BY PUMP CLOCK...

MEMORY DEVICES CONFIGURED TO PERFORM LEAK CHECKS

MEMORY DEVICES CONFIGURED TO PERFORM LEAK CHECKS

PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS

PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS