Jason M. Hart

Person

Hayden, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated pulse-control and enable latch circuit
- Patent number 8,686,778
- Issue date Apr 1, 2014
- Oracle America, Inc.
- Jason M. Hart
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Min-time hardended pulse flop
- Patent number 8,436,668
- Issue date May 7, 2013
- Oracle International Corporation
- Robert P. Masleid
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SRAM macro test flop
- Patent number 8,181,073
- Issue date May 15, 2012
- Oracle America, Inc.
- Ali Vahidsafa
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch with clocked devices
- Patent number 7,994,836
- Issue date Aug 9, 2011
- Oracle America, Inc.
- Jason M. Hart
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Precision falling edge generator
- Patent number 7,791,393
- Issue date Sep 7, 2010
- Oracle America, Inc.
- Robert P. Masleid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level shifter flip-flop
- Patent number 7,777,523
- Issue date Aug 17, 2010
- Oracle America, Inc.
- Robert P. Masleid
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single-input/dual-output sense amplifier
- Patent number 6,501,302
- Issue date Dec 31, 2002
- Sun Microsystems, Inc.
- Kyung T. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-blocking delayed clocking system for domino logic
- Patent number 6,018,254
- Issue date Jan 25, 2000
- Sun Microsystems, Inc.
- Alan C. Rogers
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for generating non-blocking delayed clocking signals for dom...
- Patent number 5,983,013
- Issue date Nov 9, 1999
- Sun Microsystems, Inc.
- Alan C. Rogers
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MIN-TIME HARDENDED PULSE FLOP
- Publication number 20120169392
- Publication date Jul 5, 2012
- Robert P. Masleid
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SRAM MACRO TEST FLOP
- Publication number 20110072326
- Publication date Mar 24, 2011
- SUN MICROSYSTEMS, INC.
- Ali Vahidsafa
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED PULSE-CONTROL AND ENABLE LATCH CIRCUIT
- Publication number 20110043260
- Publication date Feb 24, 2011
- SUN MICROSYSTEMS, INC.
- Jason M. Hart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATCH WITH SINGLE CLOCKED DEVICE
- Publication number 20100301915
- Publication date Dec 2, 2010
- SUN MICROSYSTEMS, INC.
- Jason M. Hart
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LATCH WITH CLOCKED DEVICES
- Publication number 20100301914
- Publication date Dec 2, 2010
- SUN MICROSYSTEMS, INC.
- Jason M. Hart
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LEVEL SHIFTER FLIP-FLOP
- Publication number 20100188119
- Publication date Jul 29, 2010
- SUN MICROSYSTEMS, INC.
- Robert P. Masleid
- H03 - BASIC ELECTRONIC CIRCUITRY

Jason M. Hart

Person

Patents Grantslast 30 patents

Integrated pulse-control and enable latch circuit

Min-time hardended pulse flop

SRAM macro test flop

Latch with clocked devices

Precision falling edge generator

Level shifter flip-flop

Single-input/dual-output sense amplifier

Non-blocking delayed clocking system for domino logic

Method for generating non-blocking delayed clocking signals for dom...

Patents Applicationslast 30 patents

MIN-TIME HARDENDED PULSE FLOP

SRAM MACRO TEST FLOP

INTEGRATED PULSE-CONTROL AND ENABLE LATCH CIRCUIT

LATCH WITH SINGLE CLOCKED DEVICE

LATCH WITH CLOCKED DEVICES

LEVEL SHIFTER FLIP-FLOP