Jason Steill

Person

Phoenix, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Selectively roughened copper architectures for low insertion loss c...
- Patent number 12,033,930
- Issue date Jul 9, 2024
- Intel Corporation
- Jieying Kong
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTERVENING LAYERS FOR THRU-VIA SEED METALLIZATION
- Publication number 20250006614
- Publication date Jan 2, 2025
- Rengarajan Shanmugam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID METALLIZATION SURFACES FOR INTEGRATED CIRCUIT PACKAGES
- Publication number 20250006616
- Publication date Jan 2, 2025
- Intel Corporation
- Suddhasattwa Nad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE SUBSTRATE EMBEDDED MULTI-LAYERED IN VIA CAPACITORS
- Publication number 20240222035
- Publication date Jul 4, 2024
- Intel Corporation
- Suddhasattwa Nad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A PACKAGE SUBSTRATE
- Publication number 20240188222
- Publication date Jun 6, 2024
- Intel Corporation
- Rahul MANEPALLI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED HORIZONTAL VARISTOR ON GLASS CORE FOR VOLTAGE REGULATION
- Publication number 20240113048
- Publication date Apr 4, 2024
- Intel Corporation
- Srinivasan Raman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED THIN FILM VARISTOR IN THROUGH GLASS VIAS
- Publication number 20240113046
- Publication date Apr 4, 2024
- Intel Corporation
- Jason Scott Steill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINX BASED SURFACE FINISH ARCHITECTURE
- Publication number 20240006299
- Publication date Jan 4, 2024
- Intel Corporation
- Suddhasattwa Nad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POCKETED COPPER IN FIRST LAYER INTERCONNECT AND METHOD
- Publication number 20240006291
- Publication date Jan 4, 2024
- Intel Corporation
- Suddhasattwa Nad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE HAVING ONE OR MORE ELECTRICAL INTERCONNECTS
- Publication number 20240006298
- Publication date Jan 4, 2024
- Intel Corporation
- Suddhasattwa Nad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE LITHOGRAPHY METHODS FOR INTERCONNECT ARCHITECTURES
- Publication number 20230420346
- Publication date Dec 28, 2023
- Intel Corporation
- Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYMMETRICAL DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRON...
- Publication number 20230420353
- Publication date Dec 28, 2023
- Intel Corporation
- Suddhasattwa Nad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-PATHWAY ROUTING VIA THROUGH HOLE
- Publication number 20230420298
- Publication date Dec 28, 2023
- Intel Corporation
- Suddhasattwa Nad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVELY ROUGHENED COPPER ARCHITECTURES FOR LOW INSERTION LOSS C...
- Publication number 20220102259
- Publication date Mar 31, 2022
- Intel Corporation
- Jieying Kong
- H01 - BASIC ELECTRIC ELEMENTS

Jason Steill

Person

Patents Grantslast 30 patents

Selectively roughened copper architectures for low insertion loss c...

Patents Applicationslast 30 patents

INTERVENING LAYERS FOR THRU-VIA SEED METALLIZATION

HYBRID METALLIZATION SURFACES FOR INTEGRATED CIRCUIT PACKAGES

PACKAGE SUBSTRATE EMBEDDED MULTI-LAYERED IN VIA CAPACITORS

METHOD OF FORMING A PACKAGE SUBSTRATE

INTEGRATED HORIZONTAL VARISTOR ON GLASS CORE FOR VOLTAGE REGULATION

EMBEDDED THIN FILM VARISTOR IN THROUGH GLASS VIAS

SINX BASED SURFACE FINISH ARCHITECTURE

POCKETED COPPER IN FIRST LAYER INTERCONNECT AND METHOD

SUBSTRATE HAVING ONE OR MORE ELECTRICAL INTERCONNECTS

SINGLE LITHOGRAPHY METHODS FOR INTERCONNECT ARCHITECTURES

ASYMMETRICAL DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRON...

MULTI-PATHWAY ROUTING VIA THROUGH HOLE

SELECTIVELY ROUGHENED COPPER ARCHITECTURES FOR LOW INSERTION LOSS C...