Jason Stephens

Person

Cohoes, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Middle of the line self-aligned direct pattern contacts
- Patent number 11,043,418
- Issue date Jun 22, 2021
- GLOBALFOUNDRIES U.S. INC.
- Jason E. Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Merge mandrel features
- Patent number 10,741,439
- Issue date Aug 11, 2020
- GLOBALFOUNDRIES Inc.
- Hsueh-Chung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods, apparatus and system for a passthrough-based architecture
- Patent number 10,559,503
- Issue date Feb 11, 2020
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Middle of the line self-aligned direct pattern contacts
- Patent number 10,522,403
- Issue date Dec 31, 2019
- GLOBALFOUNDRIES Inc.
- Jason E. Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Merge mandrel features
- Patent number 10,340,180
- Issue date Jul 2, 2019
- GLOBALFOUNDRIES Inc.
- Hsueh-Chung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Devices and methods for forming cross coupled contacts
- Patent number 10,262,941
- Issue date Apr 16, 2019
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus and system for a high density middle of line flow
- Patent number 10,236,350
- Issue date Mar 19, 2019
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Devices with chamfer-less vias multi-patterning and methods for for...
- Patent number 10,181,420
- Issue date Jan 15, 2019
- GLOBALFOUNDRIES Inc.
- Jason Eugene Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor contacts self-aligned in two dimensions
- Patent number 10,056,373
- Issue date Aug 21, 2018
- GLOBALFOUNDRIES Inc.
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of patterning pillars to form variable continuity cuts in in...
- Patent number 9,852,986
- Issue date Dec 26, 2017
- GLOBALFOUNDRIES Inc.
- Jason Eugene Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a high-k contact liner to improve effective via...
- Patent number 9,825,031
- Issue date Nov 21, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method of forming self-aligned cuts in mandrel and a...
- Patent number 9,818,641
- Issue date Nov 14, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a pattern for interconnection lines and associate...
- Patent number 9,818,623
- Issue date Nov 14, 2017
- GLOBALFOUNDRIES Inc.
- Jason Eugene Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method of forming self-aligned cuts in a non-mandrel...
- Patent number 9,818,640
- Issue date Nov 14, 2017
- GLOBALFOUNDRIES Inc.
- Jason Eugene Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods, apparatus and system for a passthrough-based architecture
- Patent number 9,818,651
- Issue date Nov 14, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect structure for semiconductor devices with multiple powe...
- Patent number 9,812,396
- Issue date Nov 7, 2017
- GLOBALFOUNDRIES Inc.
- Jason Eugene Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming ANA regions in an integrated circuit
- Patent number 9,786,545
- Issue date Oct 10, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compensating for lithographic limitations in fabricating semiconduc...
- Patent number 9,779,943
- Issue date Oct 3, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a pattern for interconnection lines in an integra...
- Patent number 9,691,626
- Issue date Jun 27, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor contacts self-aligned two dimensions
- Patent number 9,660,040
- Issue date May 23, 2017
- GLOBALFOUNDRIES Inc.
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical capacitors with spaced conductive lines
- Patent number 9,576,735
- Issue date Feb 21, 2017
- GLOBALFOUNDRIES Inc.
- Roderick Alan Augur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating integrated circuits using multi-patterning...
- Patent number 9,530,689
- Issue date Dec 27, 2016
- GLOBALFOUNDRIES, INC.
- Deniz Elizabeth Civay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Borderless contact formation through metal-recess dual cap integration
- Patent number 9,502,528
- Issue date Nov 22, 2016
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of cross-coupling line segments on a wafer
- Patent number 9,472,455
- Issue date Oct 18, 2016
- GLOBALFOUNDRIES Inc.
- Jason E. Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-polygon constraint decomposition techniques for use in double...
- Patent number 9,465,907
- Issue date Oct 11, 2016
- GLOBALFOUNDRIES Inc.
- Ahmed Hassan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for creating self-aligned transistor contacts
- Patent number 9,461,128
- Issue date Oct 4, 2016
- GLOBALFOUNDRIES Inc.
- Mark A. Zaleski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of modifying masking reticles to remove forbidden pitch reg...
- Patent number 9,436,081
- Issue date Sep 6, 2016
- GLOBALFOUNDRIES Inc.
- Jason Eugene Stephens
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Forming merged lines in a metallization layer by replacing sacrific...
- Patent number 9,412,655
- Issue date Aug 9, 2016
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for creating self-aligned transistor contacts
- Patent number 9,236,437
- Issue date Jan 12, 2016
- GLOBALFOUNDRIES Inc.
- Mark A. Zaleski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming cross-coupled line segments
- Patent number 9,224,617
- Issue date Dec 29, 2015
- GLOBALFOUNDRIES Inc.
- David Pritchard
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
BIPOLAR JUNCTION TRANSISTOR
- Publication number 20230352570
- Publication date Nov 2, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Mark D. Levy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIDDLE OF THE LINE SELF-ALIGNED DIRECT PATTERN CONTACTS
- Publication number 20200083102
- Publication date Mar 12, 2020
- GLOBALFOUNDRIES INC.
- Jason E. STEPHENS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MERGE MANDREL FEATURES
- Publication number 20190267281
- Publication date Aug 29, 2019
- GLOBALFOUNDRIES INC.
- Hsueh-Chung CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MERGE MANDREL FEATURES
- Publication number 20190221474
- Publication date Jul 18, 2019
- GLOBALFOUNDRIES INC.
- Hsueh-Chung CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIDDLE OF THE LINE SELF-ALIGNED DIRECT PATTERN CONTACTS
- Publication number 20190214298
- Publication date Jul 11, 2019
- GLOBALFOUNDRIES INC.
- Jason E. STEPHENS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING CONDUCTIVE LINES AND VIAS AND THE RESULTING STRU...
- Publication number 20190139823
- Publication date May 9, 2019
- GLOBALFOUNDRIES INC.
- Hsueh-Chung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICES WITH CHAMFER-LESS VIAS MULTI-PATTERNING AND METHODS FOR FOR...
- Publication number 20180226294
- Publication date Aug 9, 2018
- GLOBALFOUNDRIES INC.
- Jason Eugene STEPHENS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE
- Publication number 20180033701
- Publication date Feb 1, 2018
- GLOBALFOUNDRIES INC.
- Guillaume Bouche
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICES AND METHODS FOR FORMING CROSS COUPLED CONTACTS
- Publication number 20170309560
- Publication date Oct 26, 2017
- GLOBALFOUNDRIES INC.
- Guillaume BOUCHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A PATTERN FOR INTERCONNECTION LINES AND ASSOCIATE...
- Publication number 20170278720
- Publication date Sep 28, 2017
- GLOBALFOUNDRIES INC.
- Jason Eugene STEPHENS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE
- Publication number 20170263506
- Publication date Sep 14, 2017
- GLOBALFOUNDRIES INC.
- Guillaume Bouche
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR A HIGH DENSITY MIDDLE OF LINE FLOW
- Publication number 20170263715
- Publication date Sep 14, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPENSATING FOR LITHOGRAPHIC LIMITATIONS IN FABRICATING SEMICONDUC...
- Publication number 20170250080
- Publication date Aug 31, 2017
- GLOBALFOUNDRIES INC.
- Guillaume BOUCHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS
- Publication number 20170221886
- Publication date Aug 3, 2017
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING MULTI-PATTERNING...
- Publication number 20160300754
- Publication date Oct 13, 2016
- GLOBALFOUNDRIES, Inc.
- Deniz Elizabeth Civay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING MERGED LINES IN A METALLIZATION LAYER BY REPLACING SACRIFIC...
- Publication number 20160225666
- Publication date Aug 4, 2016
- GLOBALFOUNDRIES INC.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS
- Publication number 20160093704
- Publication date Mar 31, 2016
- Mark A. Zaleski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BORDERLESS CONTACT FORMATION THROUGH METAL-RECESS DUAL CAP INTEGRATION
- Publication number 20160064514
- Publication date Mar 3, 2016
- GLOBALFOUNDRIES INC.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR CONTACTS SELF-ALIGNED TWO DIMENSIONS
- Publication number 20160049481
- Publication date Feb 18, 2016
- GLOBALFOUNDRIES INC.
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-POLYGON CONSTRAINT DECOMPOSITION TECHNIQUES FOR USE IN DOUBLE...
- Publication number 20160026748
- Publication date Jan 28, 2016
- GLOBALFOUNDRIES INC.
- Ahmed Hassan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERTICAL CAPACITORS WITH SPACED CONDUCTIVE LINES
- Publication number 20150357120
- Publication date Dec 10, 2015
- GLOBALFOUNDRIES INC.
- Roderick Alan Augur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF CROSS-COUPLING LINE SEGMENTS ON A WAFER
- Publication number 20150287604
- Publication date Oct 8, 2015
- GLOBALFOUNDRIES INC.
- Jason E. STEPHENS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS
- Publication number 20150287636
- Publication date Oct 8, 2015
- GLOBALFOUNDRIES INC.
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MODIFYING MASKING RETICLES TO REMOVE FORBIDDEN PITCH REG...
- Publication number 20150261084
- Publication date Sep 17, 2015
- GLOBALFOUNDRIES INC.
- Jason Eugene STEPHENS
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS
- Publication number 20150236106
- Publication date Aug 20, 2015
- GLOBALFOUNDRIES INC.
- Mark A. Zaleski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING CROSS-COUPLED LINE SEGMENTS
- Publication number 20150214064
- Publication date Jul 30, 2015
- GLOBALFOUNDRIES INC.
- David PRITCHARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIDDLE-OF-THE-LINE CONSTRUCTS USING DIFFUSION CONTACT STRUCTURES
- Publication number 20150187702
- Publication date Jul 2, 2015
- GLOBALFOUNDRIES INC.
- Mahbub RASHED
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT POWER RAIL
- Publication number 20150035052
- Publication date Feb 5, 2015
- GLOBALFOUNDRIES INC.
- Jason STEPHENS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
14 LPM CONTACT POWER RAIL
- Publication number 20140246791
- Publication date Sep 4, 2014
- GLOBALFOUNDRIES INC.
- Jason Eugene STEPHENS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-ALIGNED DOUBLE PATTERNING VIA ENCLOSURE DESIGN
- Publication number 20140208285
- Publication date Jul 24, 2014
- GLOBALFOUNDRIES INC.
- Jongwook Kye
- G06 - COMPUTING CALCULATING COUNTING

Jason Stephens

Person

Patents Grantslast 30 patents

Middle of the line self-aligned direct pattern contacts

Merge mandrel features

Methods, apparatus and system for a passthrough-based architecture

Middle of the line self-aligned direct pattern contacts

Merge mandrel features

Devices and methods for forming cross coupled contacts

Method, apparatus and system for a high density middle of line flow

Devices with chamfer-less vias multi-patterning and methods for for...

Transistor contacts self-aligned in two dimensions

Method of patterning pillars to form variable continuity cuts in in...

Methods of forming a high-k contact liner to improve effective via...

Apparatus and method of forming self-aligned cuts in mandrel and a...

Method of forming a pattern for interconnection lines and associate...

Apparatus and method of forming self-aligned cuts in a non-mandrel...

Methods, apparatus and system for a passthrough-based architecture

Interconnect structure for semiconductor devices with multiple powe...

Method of forming ANA regions in an integrated circuit

Compensating for lithographic limitations in fabricating semiconduc...

Method of forming a pattern for interconnection lines in an integra...

Transistor contacts self-aligned two dimensions

Vertical capacitors with spaced conductive lines

Methods for fabricating integrated circuits using multi-patterning...

Borderless contact formation through metal-recess dual cap integration

Methods of cross-coupling line segments on a wafer

Multi-polygon constraint decomposition techniques for use in double...

Method for creating self-aligned transistor contacts

Methods of modifying masking reticles to remove forbidden pitch reg...

Forming merged lines in a metallization layer by replacing sacrific...

Method for creating self-aligned transistor contacts

Forming cross-coupled line segments

Patents Applicationslast 30 patents

BIPOLAR JUNCTION TRANSISTOR

MIDDLE OF THE LINE SELF-ALIGNED DIRECT PATTERN CONTACTS

MERGE MANDREL FEATURES

MERGE MANDREL FEATURES

MIDDLE OF THE LINE SELF-ALIGNED DIRECT PATTERN CONTACTS

METHODS OF FORMING CONDUCTIVE LINES AND VIAS AND THE RESULTING STRU...

DEVICES WITH CHAMFER-LESS VIAS MULTI-PATTERNING AND METHODS FOR FOR...

METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE

DEVICES AND METHODS FOR FORMING CROSS COUPLED CONTACTS

METHOD OF FORMING A PATTERN FOR INTERCONNECTION LINES AND ASSOCIATE...

METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE

METHOD, APPARATUS AND SYSTEM FOR A HIGH DENSITY MIDDLE OF LINE FLOW

COMPENSATING FOR LITHOGRAPHIC LIMITATIONS IN FABRICATING SEMICONDUC...

TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS

METHODS FOR FABRICATING INTEGRATED CIRCUITS USING MULTI-PATTERNING...

FORMING MERGED LINES IN A METALLIZATION LAYER BY REPLACING SACRIFIC...

METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS

BORDERLESS CONTACT FORMATION THROUGH METAL-RECESS DUAL CAP INTEGRATION

TRANSISTOR CONTACTS SELF-ALIGNED TWO DIMENSIONS

MULTI-POLYGON CONSTRAINT DECOMPOSITION TECHNIQUES FOR USE IN DOUBLE...

VERTICAL CAPACITORS WITH SPACED CONDUCTIVE LINES

METHODS OF CROSS-COUPLING LINE SEGMENTS ON A WAFER

TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS

METHODS OF MODIFYING MASKING RETICLES TO REMOVE FORBIDDEN PITCH REG...

METHOD FOR CREATING SELF-ALIGNED TRANSISTOR CONTACTS

FORMING CROSS-COUPLED LINE SEGMENTS

MIDDLE-OF-THE-LINE CONSTRUCTS USING DIFFUSION CONTACT STRUCTURES

CONTACT POWER RAIL

14 LPM CONTACT POWER RAIL

SELF-ALIGNED DOUBLE PATTERNING VIA ENCLOSURE DESIGN